AI Comes to ASICs in Data Centers
eSilicon helped Nervana design its first-gen AI ASIC
6/6/2018 04:01 PM EDT
MADISON, Wis. — Three years ago, when AI chip startup Nervana ventured into the uncharted territory of designing custom AI accelerators, the company’s move was less perilous than it might have been, thanks to an ASIC expert that Nervana — now owned by Intel — sought for help.
That ASIC expert was eSilicon.
Two industry sources independently told EE Times that eSilicon worked on Nervana’s AI ASIC and delivered it to Intel after the startup was sold. eSilicon, however, declined to comment on its customer.
To read the full article, click here
Related Semiconductor IP
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
- JESD204E Controller IP
Related News
- QuickLogic Announces $1M eFPGA Hard IP Contract for Data Center ASIC
- Ceva Partners with Microchip Technology to Enable AI Acceleration Across Edge Devices and Data Center Infrastructure
- Arm Neoverse platform integrates NVIDIA NVLink Fusion to accelerate AI data center adoption
- QuickLogic eFPGA Hard IP Selected by Chipus for 12 nm High Performance Data Center ASIC
Latest News
- Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
- A new CEO, a cleared deck: Is Imagination finally ready for a deal?
- SkyeChip’s UCIe 3.0 Advanced Package PHY IP for SF4X Listed on Samsung Foundry CONNECT
- Victor Peng Joins Rambus Board of Directors
- Arteris Announces Financial Results for the Fourth Quarter and Full Year 2025 and Estimated First Quarter and Full Year 2026 Guidance