AI Comes to ASICs in Data Centers
eSilicon helped Nervana design its first-gen AI ASIC
Junko Yoshida
6/6/2018 04:01 PM EDT
MADISON, Wis. — Three years ago, when AI chip startup Nervana ventured into the uncharted territory of designing custom AI accelerators, the company’s move was less perilous than it might have been, thanks to an ASIC expert that Nervana — now owned by Intel — sought for help.
That ASIC expert was eSilicon.
Two industry sources independently told EE Times that eSilicon worked on Nervana’s AI ASIC and delivered it to Intel after the startup was sold. eSilicon, however, declined to comment on its customer.
To read the full article, click here
Related Semiconductor IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
Related News
- QuickLogic Announces $1M eFPGA Hard IP Contract for Data Center ASIC
- QuickLogic eFPGA Hard IP Selected by Chipus for 12 nm High Performance Data Center ASIC
- Marvell to Acquire XConn Technologies, Expanding Leadership in AI Data Center Connectivity
- Socionext Collaborates with Arm to Advance AI Data Center Infrastructure with Arm Total Design
Latest News
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware