Actel plans to produce FPGAs as ASIC cores
Actel plans to produce FPGAs as ASIC cores
By Craig Matsumoto, EE Times
June 5, 2000 (12:36 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000605S0021
SAN JOSE, Calif. Actel Corp. is making its bid to provide small field-programmable gate arrays as ASIC cores. The company's technology, garnered through two acquisitions, follows the lead of LSI Logic Corp.'s eFPGA program. Actel will provide both SRAM- and flash-based cores, which will be fit into a standard ASIC design flow with the help of EDA partnerships not finalized at press time. While not revealing any release dates, Actel officials will be discussing their product plans at this week's Design Automation Conference in Los Angeles. Multiple companies have discussed combining programmable circuitry with fixed system logic. Actel's approach is closest to LSI Logic's, in which small programmable cores are dropped into ASICs to add flexibility. Other companies such as FPGA leaders Xilinx Inc. and Altera Corp. are working with larger blocks of programmability. Their goal is to develop system-on-chip offerings that revolve around large F PGAs seeded with intellectual-property cores. Actel, like LSI Logic, believes that only small amounts of programmability are required in most designs. And despite LSI Logic's heft, Actel believes the density of its core, as well as its compatibility with the ASIC design flow, will give it an edge. Proven architecture "We don't feel threatened by anything we see out there," said Dennis Kish, vice president of strategic marketing for Actel. "The architecture for both [of our] cores is proven in silicon, and we have a robust tool set for each." Key to Actel's program are the considerations being made to keep the embedded FPGA accessible after fabrication. Early microprocessor cores lacked that kind of accessibility. Actel also had to develop an interface between the FPGA core and the rest of the chip. Also important was finding a way to pin-fix the FPGA core, so the core could be reprogrammed without altering the rest of the chip, Kish said. The core is also being furnished with built-in-self-test circuitry. Actel's cores come from its purchases of GateField Corp. and Prosys Technology, although the latter deal had not been finalized at press time. Prosys will be supplying the SRAM-based FPGA core for Actel. GateField developed the flash-based FPGA architecture used in Actel's ProASIC product line. Actel had an equity stake in GateField and purchased the rest of the company on May 11. GateField now is adapting its technology to produce a flash-based FPGA core, which Actel wants because of the lower die size of flash compared with SRAMs. Although no release dates are being disclosed, Actel does claim that its cores are well along the development track. "Both players [Prosys and GateField] have been talking about this kind of model for quite some time," Kish said.
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Related News
- Nextera-Adeas ST 2110 IP cores are now available on Intel FPGAs
- Mitel taps IBM to produce PowerPC-based digital TV chips
- TSMC and BOPS Team to Produce Highest-Performance, Programmable, Single-Chip DSP Chip in Industry
- Intel says it has no plans to license Wireless MMX
Latest News
- Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms