3-D Stacking Reaches New Heights : Tachyon Semiconductor Creates Four-Wafer Stack
Naperville, IL - February 7, 2003 - The semiconductor industry has reached a new milestone with the creation of a 3-D silicon structure built of four silicon wafers. Tachyon Semiconductor Corporation, which created the four-wafer stack in August of 2002, believes it to be the very first multi-wafer stack ever achieved. Previous stacking announcements (by Tachyon and others) have described the bonding of only two silicon wafers.
Wafer stacking is of great interest to semiconductor manufacturers, who hope to build fast, dense multi-layer devices by using wafer stacks. In addition to speed and density, 3-D silicon devices promise lower power consumption and higher optimization than 2-D chips.
The ground-breaking four-wafer stack was created to test stress management parameters, the integrity of multiple interfaces, the results of ultra-thinning, and the mechanical dicing process that will cut wafer stacks into stacked chips. Variable bonding surfaces were incorporated in order to investigate several engineering issues, and voids were deliberately introduced to test a non-destructive void detection and calibration technique. The results of the tests, Tachyon says, amply confirmed the viability of their stacking process and demonstrated the potential to incorporate virtually any number of layers.
Tachyon's unique stacking process uses copper-to-copper thermal diffusion to bond standard silicon wafers without introducing any adhesives or dielectric materials. After the first two wafers are bonded, the top wafer is thinned to 5 microns; additional wafers are bonded and thinned in turn. The extreme thinning facilitates through-wafer electrical connections and heat dissipation; it also ensures that future multi-layer devices will fit into standard packaging.
Tachyon Semiconductor Corporation is a privately held fabless semiconductor and engineering design services company that has developed significant intellectual property concerning stacked memory and stacked SOC (System-On-a-Chip) integrated circuits. To learn more about Tachyon's technology, visit www.tachyonsemi.com on the World Wide Web.
# # #
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related News
- Wafer Stacking Technology Promises Faster, Denser System-On-a-Chip (SOC)
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale
- Silicon Wafer Shipments Drop to Lowest Level Since Fourth Quarter of 2017
- Silicon Wafer Area Shipments Fall for Fourth Consecutive Quarter
Latest News
- Jim Keller: ‘Whatever Nvidia Does, We’ll Do The Opposite’
- FlexGen Streamlines NoC Design as AI Demands Grow
- IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
- Global Semiconductor Sales Increase 2.5% Month-to-Month in April
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload