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IPsec and TLS Engine IP

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Compare 15 IPsec and TLS Engine IP from 9 vendors (1 - 10)
  • IPsec Engine

    • The IPsec Engine implements RFC4301 and other relevant RFCs, providing confidentiality, connectionless data integrity, data-origin authentication and replay protection on OSI layer 3.

    Block Diagram -- IPsec Engine
  • Network Security Crypto Accelerator
    • The Network Security Crypto Accelerator is a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • This IP is used to accelerate/offload MACsec, IPsec, VPN, TLS/SSL, disk encryption, or any other custom application, requiring symmetric cryptography algorithms.
    Block Diagram -- Network Security Crypto Accelerator
  • IPsec ESP IP core for FPGA
    • Built on the success of Helion's industry proven cryptographic IP cores, the Helion ESP Engine provides hardware acceleration of the key cryptographic algorithms and packet processing required by the IPsec Encapsulating Security Payload (ESP) protocol.
    • Its modular architecture provides the flexibility to support only those cryptographic algorithms required for a particular application to provide the optimum logic area and performance trade-off.
    Block Diagram -- IPsec ESP IP core for FPGA
  • Message filter
    • Message filters are placed in the middle of a TCP / TLS session to scan application data, and discard unwanted messages and security-issue packets, reducing unnecessary traffic without increasing CPU load or latency.
    • Unlike filters by IP address or port, which scan the data content and discard or pass through packets, DPI (Deep Packet Inspection) and other methods tend to cause CPU processing load and packet processing delays.
    Block Diagram -- Message filter
  • SSL/TLS Offload Engine
    • Our SSL/TLS engine accelerates and offloads processing for encryption / decryption and authentication in SSL / TLS by combining our TCP offload and crypt engine.
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    • Since the record layer processing is completely hardware offloaded, the user application can overwhelmingly reduce the CPU load which only needs preparing the data to transfer securely.
    Block Diagram -- SSL/TLS Offload Engine
  • TLS - Validates TLS protocols to ensure secure, encrypted data transmission
    • TLS Verification IP (VIP) ensures secure communication by validating TLS protocol implementations. It simulates handshake processes, tests encryption, and verifies data integrity to protect against cyber threats during data transmission.
    • This product finds application in web browsing, email security, VPNs, cloud services, mobile apps, and more. It safeguards sensitive data across various platforms, ensuring end-to-end encryption and robust protection in diverse network environments
    Block Diagram -- TLS - Validates TLS protocols to ensure secure, encrypted data transmission
  • Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
    • 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
    Block Diagram -- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
  • Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
    • 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
    Block Diagram -- Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
  • Multi-Protocol Engine, Look-Aside, 1 Gbps
    • Protocol-aware IPsec/TLS packet engine with Look-Aside interface for IoT.
    • Up to 1 Gbps, lowest gate count in the industry, just 100K gates (ex AMBA interface).
    • Supported by Driver Development Kit, QuickSec IPsec toolkit, Secure Boot Toolkit.
    Block Diagram -- Multi-Protocol Engine, Look-Aside, 1 Gbps
  • TLS 1.3 Compliant Crypto Coprocessor
    • NIST CAVP certified and OSCCA standard compliant crypto engine suite
    • Includes private/public key ciphers, message authentication code, hashes, and key derivation
    • Key wrapping function for the secure export of keys
    • Public-key coprocessor for digital signatures and key agreements over elliptic/Edward curves
    Block Diagram -- TLS 1.3 Compliant Crypto Coprocessor
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