IP Catalog > Security IP > Cryptography IP > Public Key Accelerator IP > Other

Other

All offers in Other
Filter
Filter

Login required.

Sign in

Search (16)
Compare 16 Other from 8 vendors (1 - 10)
  • ASCON Authenticated Encryption & Hashing Engine
    • The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) and hashing algorithms described in the Ascon v1.2 specification. 
    • A single instance of the ASCON-F IP core can encrypt or decrypt data using the Ascon-128 and Ascon-128a functions or perform Cryptographic hashing Hash per the Ascon-Hash and Ascon-Hasha functions.
    Block Diagram -- ASCON Authenticated Encryption & Hashing Engine
  • Public Key Accelerator
    • Modular exponentiation operations with up to 4096-bit modulus
    • Prime field ECC operations with up to 571-bit modulus
    • Fastest implementation is 58 kGE and 68 Op/s for 2048-bit RSA, 431 Op/s for 1024-bit RSA, 150 Op/s for 384-bit scalar multiplication
    Block Diagram -- Public Key Accelerator
  • NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
    • Minimal Resource Requirements
    • Secure Architecture
    • FIPS 186-4 and SP 800-56A compliant
    Block Diagram -- NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
  • Curve25519 Key Exchange and Digital Signature IP Core
    • Minimal Resource Requirements: The entire XIP4003C requires less than 800 ALMs (Cyclone® 5) and uses only 1-2 multipliers/DSP Blocks2 and 1-2 internal memory block in a typical FPGA implementation.
    • Constant Latency: The execution time of XIP4003C is independent of the key value, and consequently provides protection against timing-based side-channel attacks.
    • Performance: Despite its small size, XIP4003C can support more than 100 key exchange or digital signature operations per second.
    • Standard Compliance: XIP4003C is compliant with RFC7748, RFC8032, and the draft version of FIPS 186-5. XIP4003C can be used as a part of many public-key protocols including IKEv2 (RFC 8031) and TLS 1.3 (RFC 8446).
    Block Diagram -- Curve25519 Key Exchange and Digital Signature IP Core
  • Curve25519 Key Exchange IP Core
    • Minimal Resource Requirements: The entire XIP4001C requires less than 1k Logic Elements and uses only 1-2 multipliers/DSP Blocks2 and one internal memory block in a typical FPGA implementation.
    • Constant Latency: The execution time of XIP4001C is independent of the key value, and consequently provides protection against timing-based side-channel attacks.
    • Performance: Despite its small size, XIP4001C can support more than 100 key exchange operations per second.
    • Standard Compliance: XIP4001C is compliant with RFC7748, and can be used as a part of many public-key protocols including IKEv2 (RFC 8031) and TLS 1.3 (RFC 8446).
    Block Diagram -- Curve25519 Key Exchange IP Core
  • Ascon, A Lightweight Cryptographic Suite for AEAD and Hashing
    • Small Resource Requirements
    • Versatile Algorithm Support
    • Secure Architecture
    Block Diagram -- Ascon, A Lightweight Cryptographic Suite for AEAD and Hashing
  • Elliptic Curve Digital Signature generation and verification
    • Supports any EC over GF(p) of the simplified Weierstrass form that is commonly defined in ECC standards such as NIST, SEC2, Brainpool
  • 32-bit Public Key Accelerator
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • 128-bit Public Key Accelerator
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
×
Semiconductor IP