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ML-DSA

ML-DSA (FIPS 204, formerly CRYSTALS-Dilithium): This algorithm is also based on lattice problems but is specifically designed for digital signatures, offering strong security guarantees and efficient performance.

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Compare 18 ML-DSA from 9 vendors (1 - 10)
  • Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
    • The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
    Block Diagram -- Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
  • ML-KEM / ML-DSA Post-Quantum Cryptography IP
    • ML-KEM (Crystals-Kyber) and ML-DSA (Crystals-Dilithium) are Post-Quantum Cryptographic (PQC) algorithms, meaning they are mathematically designed to be robust against a cryptanalytic attack using a quantum computer.
    • Both have been standardized by the NIST in it post-quantum cryptography project.
    Block Diagram -- ML-KEM / ML-DSA Post-Quantum Cryptography IP
  • Single instance HW Lattice PQC ultra accelerator
    • PQPerform-Flare is a powerful hardware-based FIPS 140-3 CAVP-certified product, designed for high throughput and low latency PQC.
    •  It adds PQC for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs.
    Block Diagram -- Single instance HW Lattice PQC ultra accelerator
  • Highly configurable HW Lattice PQC ultra acceleration in AXI4 & PCIe systems
    • PQPerform-Inferno is a powerful, scalable hardware solution engineered for unparalleled performance in the post-quantum era.
    • As a FIPS 140-3 CAVP-certified product, it provides a trusted foundation for next-generation security.
    Block Diagram -- Highly configurable HW Lattice PQC ultra acceleration in AXI4 & PCIe systems
  • PQPerform-Inferno + RISC-V processor for enhanced crypto-agility
    • PQPerform-Flex provides robust and agile high-performance acceleration for the ML-KEM and ML-DSA post-quantum cryptographic algorithms but also future standards (programmable post-silicon, such as HQC), designed for seamless integration into modern SoC designs for both ASIC and FPGA targets.
    Block Diagram -- PQPerform-Inferno + RISC-V processor for enhanced crypto-agility
  • CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
    • Hardware core for accelerating the high-level operations specified in the NIST FIPS 204 standard.
    Block Diagram -- CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
  • APB Post-Quantum Cryptography Accelerator IP Core
    • Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
    • The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
    Block Diagram -- APB Post-Quantum Cryptography Accelerator IP Core
  • Falcon IP Core
    • Falcon IP Core is a post-quantum digital signature algorithm (DSA).
    • It is currently under development. It is going to be compliant with Falcon specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    • Additionally, Falcon IP Core will be enhanced to achieve compliance with NIST Falcon Standart when it is released. 
    Block Diagram -- Falcon IP Core
  • Dilithium IP Core
    • Dilithium IP Core is a post-quantum digital signature algorithm (DSA).
    • It currently supports Sign and Verify functions, with key generation functionality planned for future implementation.
    • This IP is compliant with Dilithium specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    Block Diagram -- Dilithium IP Core
  • Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
    • PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
    • With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
    Block Diagram -- Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
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