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CXL IP

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Compare 253 IP from 25 vendors (1 - 10)
  • CXL Controller
    • Compliant with CXL Specification version 2.0/1.1 and PCIe Base Specification 5.0 (32 Gbps per lane)
    • Complaint with PIPE 5.x interface
    • Supports X16, X8, X4, X2 and X1 lane widths
    • Supports 512, 256 and 128 Data path widths
    • Supports PCI Express Alternate Protocol
  • CXL 3.2 Verification IP
    • Compliant with the CXL 3.2, 2.0 & 1.1 Specification.
    • Support for all three protocols CXL.IO, CXL.CACHE & CXL.MEM including all CXL device types
    • Support for PCIE Mode & Alternate Protocol Negotiation for CXL Mode
    • Support for 256B flit in 64GT/s with PCIe Gen 6 as well as 32/16/8 GT/s speeds with backward compatibility.
    Block Diagram -- CXL 3.2 Verification IP
  • Verification IP for CXL
    • Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CXL3, CXL3.1
    Block Diagram -- Verification IP for CXL
  • Compute Express Link (CXL) FPGA IP
    • Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
    • First FPGA to pass CXL Consortium Compliance Program (up to 32 GT/s speed).
    Block Diagram -- Compute Express Link (CXL) FPGA IP
  • CXL - Enables robust testing of CXL-based systems for performance and reliability
    • CXL Verification IP is a cutting-edge solution for validating designs based on the Compute Express Link (CXL) protocol. With features like protocol compliance checks, cache coherency validation, and advanced debugging tools, it ensures robust and efficient testing of high-performance computing systems.
    • From HPC and AI to automotive and edge computing, CXL Verification IP supports diverse applications. It enables seamless communication between processors, memory, and accelerators, ensuring reliable performance in data centers, ML systems, cloud infrastructures, and telecom networks.
    Block Diagram -- CXL - Enables robust testing of CXL-based systems for performance and reliability
  • CXL Controller IP
    • The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
    • Possessing high customizability and supportability, this controller provides a comprehensive CXL solution.
    Block Diagram -- CXL Controller IP
  • Simulation VIP for CXL
    • Device Configuration
    • Host, Device
    • Spec Version
    • 1.1, 2.0, 3.0
    Block Diagram -- Simulation VIP for CXL
  • CXL 3 Controller IP
    • The CXL 3 Controller IP is designed to support dual-mode operation, allowing dynamic selection between host and device modes.
    • It connects to standard 64GT/s PHYs through the PIPE 6.x interface and supports high data rates across various link widths.
    Block Diagram -- CXL 3 Controller IP
  • CXL Verification IP
    • Supports CXL specs revision 1.0, 1,1 and 2.0.
    • Supports Native PCIe mode and below features as defined in the PCIe specification.
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0/5.1
    • Serial, PIPE, PCS/PMA, Low pin count and SerDes interface
    Block Diagram -- CXL Verification IP
  • CXL CONTROLLER IIP
    • Compliant with CXL 1.0/1.1 Specifications
    • Supports Native PCIe mode and below features as defined in the PCIe specification
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • PIPE interface
    Block Diagram -- CXL CONTROLLER IIP
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