The Cadence® Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®). Built on top of Cadence's mature industry-leading VIP for PCIe, the CXL VIP provides a complete bus functional model for all three CXL protocols, CXL.io/CXL.mem/CXL.cache, and allows users to verify both CXL host and device designs for all device types (Type 1 – 3) from the very first days of the CXL protocol.
Designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system level, the VIP for CXL runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development, and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.
With a layered architecture and powerful callback mechanism, verification engineers can verify CXL features at each functional layer (PHY, link, transport, and application layer) and create highly targeted designs while taking advantage of the latest design methodologies for random testing to cover a larger verification space. The VIP for CXL can be used as a standalone and as a platform for running TripleCheck tests and supports the latest PIPE specification.
Supported specifications: Compute Express Link Specification 2.0 revision 1.0 and 3.0 revision 1.0.
