silvaco IP

Silvaco develops General Purpose I/O optimized for design flexibility, performance and ESD protection. We also provide specialty I/O, such as high speed LVDS (2Gbs) and SSTL, plus I/O for cryogenic applications.

• The Standard Cell libraries deliver thousands of highly optimized cells with each one being optimized for power, area, speed, routing, and yield.
• These libraries may be extended with Power Management Kits, taking power reduction to the next level, and ECO Kits to enable late-stage design modifications.

• Nominal voltage of 0.75 V +/-10 %
• Low voltage of 0.45 V +/-10 %
• Track height: 7.5T
• Operating temperature: -40°C to 125°C

• The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache architecture.
• This architecture enhances system performance, scalability, power efficiency, data locality, application responsiveness, cost optimization, and market competitiveness, providing a distinctive business value.

• Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
• Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
• Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power

• Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.

• The ColdFire® V1 Platform (CFV1P) is a fully configurable micro controller subsystem built from the same ColdFire V1 processor IP that is implemented in ColdFire+ family devices from Freescale Semiconductor.
• The ColdFire V1 Platform extends the core processor platform used in Freescale’s MCF51Qx and MCF51Jx devices to include a set of production-proven peripheral modules, each of which can be included in or excluded from your ColdFire V1 Platform implementation depending on your system requirements.

• IEEE 1149.1 interface to existing test/debug hardware
• IEEE 1149.7 interface to target system(s)
• Supports all IEEE 1149.7 scan formats
• Supports all IEEE 1149.7 scan topologies

• Supports IEEE 1149.7 classes 0–5 (selected through hardware configuration parameter)
• Partitioned along IEEE 1149.7-specified functional boundaries (so that only the required hardware is included):
• Supports all mandatory and optional scan formats: JScan0–3, SScan0–3, OScan0–7, and MScan
• Supports all mandatory and optional cJTAG commands

• Variable-length RISC, clock-multiplied core
• 166-MHz in typical 130-nm process
• Independent, decoupled pipelines: 2-stage instruction fetch pipeline (IFP); 2-stage operand execution pipeline (OEP); FIFO instruction buffer is the decoupling mechanism
• 16 user-accessible, 32-bit general purpose registers (GPRs)