The IEEE 1149.7 Compact TAP from Silvaco provides an IEEE 1149.7-compliant Test Access Port (TAP), enabling you to take advantage of IEEE 1149.7 features such as:
- 2-pin access to your on-chip IEEE 1149.1 test infrastructure
- Reduced scan times through shorter scan paths
- Efficient use of the 2-pin interface for both test and debug
The IEEE 1149.7 Compact TAP supports all mandatory and optional features of IEEE Std. 1149.7-2009 and is the cornerstone of the emerging Compact JTAG ecosystem—implemented in chips from Texas Instruments and other major semiconductor manufacturers and the reference design used by leading development system providers.
cjTAG IEEE 1149.7 Compact TAP Controller
Overview
Key Features
- Supports IEEE 1149.7 classes 0–5 (selected through hardware configuration parameter)
- Partitioned along IEEE 1149.7-specified functional boundaries (so that only the required hardware is included):
- Extended Processing Unit (EPU) for class 0–3 operation
- Advanced Processing Unit (APU) for class 4–5 operation
- Further partitioning within EPU and APU for class-specific and optional features
- Separate blocks for clock and reset signal conditioning
- Supports all mandatory and optional scan formats: JScan0–3, SScan0–3, OScan0–7, and MScan
- Supports all mandatory and optional cJTAG commands
- Firewall provides robust hot-connection by disabling TCK until firewall is disabled by the Debug Test System (DTS)
Block Diagram
Deliverables
- Synthesizable Verilog source code
- Integration testbench and tests
- Documentation
- Scripts for simulation and synthesis with support for common EDA tools
Technical Specifications
Maturity
Silicon Proven
Availability
Now