interconnect IO IP
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203
IP
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31
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High-scalable, high-performance Interconnect fabric IP with cache coherence support
- High bandwidth, low power consumption, low latency
- Support Component Aggregation Layer (CAL)
- Topology: Mesh
- Support multiple I/O Coherent Master Nodes (CIO)
- Maximum node count: 12x12
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Interconnect fabric IP with cache coherence support
- StarNoC-500 is the vendor's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC.
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AXI Interconnect
- The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs.
- AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4
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Rapid IO 4.0/3.1/2.2 PHY
- 4 Channel per Quad
- Shared Quad common PLL architecture
- Digitally-control-impedance termination resistors
- Configurable TX output differential voltage swing
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IO 3.3V LVDS Rx Automotive Grade 2 in GF (12nm)
- Maximum operating speed: up to 3.4GBPS
- Compatibility with TIA/EIA - 644-A for greater interoperability
- Loop back option supported for both Pre/Post driver in LVDS TX
- HBM 2KV, CDM 500V (up to 7A)
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IO 1.8V LVDS Rx in GF (12nm)
- Maximum operating speed: up to 3.4GBPS
- Compatibility with TIA/EIA - 644-A for greater interoperability
- Loop back option supported for both Pre/Post driver in LVDS TX
- HBM 2KV, CDM 500V (up to 7A)
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IO 3.3V LVDS Rx in GF (12nm)
- Maximum operating speed: up to 3.4GBPS
- Compatibility with TIA/EIA - 644-A for greater interoperability
- Loop back option supported for both Pre/Post driver in LVDS TX
- HBM 2KV, CDM 500V (up to 7A)
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IO 1.8V LVDS Automotive Grade 1 GF (22nm)
- Maximum operating speed: up to 3.4GBPS
- Compatibility with TIA/EIA - 644-A for greater interoperability
- Loop back option supported for both Pre/Post driver in LVDS TX
- HBM 2KV, CDM 500V (up to 7A)
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IO 1.8V LVDS in GF (22nm)
- Maximum operating speed: up to 3.4GBPS
- Compatibility with TIA/EIA - 644-A for greater interoperability
- Loop back option supported for both Pre/Post driver in LVDS TX
- HBM 2KV, CDM 500V (up to 7A)
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Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
- Ethernet/ARINC664P7 Switch with customizable number of ports up to 1 Gbps.
- Support IEEE 1588 PTPV2 as GrandMaster or User
- Safe & Secure Ethernet communication
- Multi-protocol : CAN, ARINC429, MIL-STD-1553, TSN