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interconnect IO IP

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Compare 194 IP from 27 vendors (1 - 10)
  • AXI Interconnect
    • The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs.
    • AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4
    Block Diagram -- AXI Interconnect
  • Rapid IO 4.0/3.1/2.2 PHY
    • 4 Channel per Quad
    • Shared Quad common PLL architecture
    • Digitally-control-impedance termination resistors
    • Configurable TX output differential voltage swing
    Block Diagram -- Rapid IO 4.0/3.1/2.2 PHY
  • IO 3.3V LVDS Rx Automotive Grade 2 in GF (12nm)
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • IO 1.8V LVDS Rx in GF (12nm)
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • IO 3.3V LVDS Rx in GF (12nm)
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • IO 1.8V LVDS Automotive Grade 1 GF (22nm)
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • IO 1.8V LVDS in GF (22nm)
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
    • Ethernet/ARINC664P7 Switch with customizable number of ports up to 1 Gbps.
    • Support IEEE 1588 PTPV2 as GrandMaster or User
    • Safe & Secure Ethernet communication
    • Multi-protocol : CAN, ARINC429, MIL-STD-1553, TSN
    Block Diagram -- Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
  • Physical Layer Interface Core
    • Fully Compliant with Rapid Interconnect Specification Rev 1.1, 3/2001 prescribed by Rapid Trade Association.
    • 32-bit standard Host/Link Interface.
    • Full Duplex Independent Transmit and Receive Data Path.
    • Dual Data Rate (DDR): 62.5-125 MHz.
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