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Compare 11 IP from 6 vendors (1 - 10)
  • ACAP HDR Image Signal Processing Framework
    • Complete HDR ISP video processing framework for multi-channel vision and AI systems
    • Demonstrates logicBRICKS HDR ISP pipeline for parallel processing of three UHD automotive video cameras
    • Fully compatible with Xylon logiIVID-ACAP-ISP HDR ISP Evaluation Kit for Versal ACAP based on AMD-Xilinx ACAP Versal VCK190 Evaluation Kit
    • Runs on Linux OS, includes logicBRICKS software drivers and demo applications made with AMD-Xilinx Vitis™ Unified Software Platform 2021.2
    Block Diagram -- ACAP HDR Image Signal Processing Framework
  • Compute IP
    • OpenCL3.0
    • OpenCV
    • OpenVX1.3
    • Shader Cores: 64
  • Cost-efficiency, AI-based noise reduction IP
    • The AI-NR series IPs offer noise reduction solutions for optimizing image quality in low-light or complex lighting conditions.
    • Currently consisting of the AINR1000 and AINR2000 IPs, this series is capable of significantly reducing image noise while preserving rich picture details and color fidelity, providing superior performance for optimizing image quality in low-light or complex lighting conditions.
    • With dynamic noise processing technology, the AINR1000 efficiently handles not only static noise but also motion noise in video, ensuring clear and smooth visuals at all times.
    Block Diagram -- Cost-efficiency, AI-based noise reduction IP
  • Visibility Improver IP
    • Improves the visibility in various shooting conditions.
    • Supports both AXI4-stream I/F and DE (data enable) I/F as input/output video interface.
    • Selectable starting by software or hardware event.
    Block Diagram -- Visibility Improver IP
  • HDR ISP framework for multi-camera applications
    • Complete HDR ISP video processing framework for multi-channel vision and AI systems
    Block Diagram -- HDR ISP framework for multi-camera applications
  • WDR (Shadow and Highlight Compensation Core)
    • Automatically generate the tone curves depending on a scene
    • Preserve the local contrast, detail and true color
    • Wide dynamic range function without frame memories
    • Backlight , shadow and highlight image compensation
  • 32-bit Basic Application Processor
    • The royalty free BA22-AP is a 32-bit processor for demanding embedded applications that use off-chip instruction and data memories and that may need to run a real-time operating system (RTOS) or a full operating system such as Linux or Android.
    • Part of the royalty-free BA22 family, this processor core is extremely competitive in terms of high performance and low power consumption and has best-in-class code density.
    Block Diagram -- 32-bit Basic Application Processor
  • 32-bit Deeply Embedded Processor
    • The royalty free BA22-DE is a compact yet powerful 32-bit processor for deeply embedded applications.
    • It is a Harvard-style processor able to run at relatively high clock frequencies (more than 800MHz in 28nm), with a surprisingly small silicon footprint (base version is just 15K gates).
    • Highly configurable to allow a variety of size/performance trade-offs, the BA22-DE can be used as a microcontroller in numerous applications, including mixed signal processing, portable and wireless devices, and automotive systems.
    Block Diagram -- 32-bit Deeply Embedded Processor
  • Block Convolutional Encoder
    • Compatible with the following standards: IEEE 802.16-2004, IEEE 802.11a, 3GPP, 3GPP2 and DVB-S
    • Supports both continuous and block encoding
    • Variable constraint length from 3 to 9
    • Supports both internal and external tail adding in Tail Biting mode
    Block Diagram -- Block Convolutional Encoder
  • 32-bit Cache-Enabled Embedded Processor
    • The royalty-free BA22-CE is a 32-bit processor for deeply embedded applications that use off-chip instruction and data memories and that may need to run a real-time operating system (RTOS).
    • This processor core is extremely competitive in terms of high performance and low power consumption, and has best-in-class code density.
    Block Diagram -- 32-bit Cache-Enabled Embedded Processor
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Semiconductor IP