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image cognition IP

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Compare 14 IP from 8 vendors (1 - 10)
  • ACAP HDR Image Signal Processing Framework
    • The ACAP HDR Image Signal Processing Framework is intended to showcase a complete logicBRICKS IP suite implementation of High-Dynamic Range (HDR) Image Signal Processing (ISP) pipeline in an embedded design based on AMD-Xilinx ACAP programmable devices.
    • The HDR ISP pipeline enables crisp camera video under altering and rough lighting conditions in next generation multi-channel embedded systems for use in automotive, surveillance, medical, aerospace and similar video and vision AI applications.
    Block Diagram -- ACAP HDR Image Signal Processing Framework
  • Compute IP
    • OpenCL3.0
    • OpenCV
    • OpenVX1.3
    • Shader Cores: 64
  • Cost-efficiency, AI-based noise reduction IP
    • The AI-NR series IPs offer noise reduction solutions for optimizing image quality in low-light or complex lighting conditions.
    • Currently consisting of the AINR1000 and AINR2000 IPs, this series is capable of significantly reducing image noise while preserving rich picture details and color fidelity, providing superior performance for optimizing image quality in low-light or complex lighting conditions.
    • With dynamic noise processing technology, the AINR1000 efficiently handles not only static noise but also motion noise in video, ensuring clear and smooth visuals at all times.
    Block Diagram -- Cost-efficiency, AI-based noise reduction IP
  • Visibility Improver IP
    • Improves the visibility in various shooting conditions.
    • Supports both AXI4-stream I/F and DE (data enable) I/F as input/output video interface.
    • Selectable starting by software or hardware event.
    Block Diagram -- Visibility Improver IP
  • Neuromorphic Processor IP (Second Generation)
    • Supports 8-, 4-, and 1-bit weights and activations
    • Programmable Activation Functions
    • Skip Connections
    • Support for Spatio-Temporal and Temporal Event-Based Neural Network
    Block Diagram -- Neuromorphic Processor IP (Second Generation)
  • Video and Vision Processing Suite
    • The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs
    • These Intel® FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, industrial inspections and robotics, smart city/retail and consumer.
    Block Diagram -- Video and Vision Processing Suite
  • Neuromorphic Processor IP
    • Supports 4-, 2-, and 1-bit weights and activations
    • Supports multiple layers simultaneously
    • Convolutional Neural Processor (CNP) and
    • Fully-connected Neural Processor (FNP)
    Block Diagram -- Neuromorphic Processor IP
  • HDR ISP framework for multi-camera applications
    • Complete HDR ISP video processing framework for multi-channel vision and AI systems
    Block Diagram -- HDR ISP framework for multi-camera applications
  • WDR (Shadow and Highlight Compensation Core)
    • Automatically generate the tone curves depending on a scene
    • Preserve the local contrast, detail and true color
    • Wide dynamic range function without frame memories
    • Backlight , shadow and highlight image compensation
  • 32-bit Basic Application Processor
    • The royalty free BA22-AP is a 32-bit processor for demanding embedded applications that use off-chip instruction and data memories and that may need to run a real-time operating system (RTOS) or a full operating system such as Linux or Android.
    • Part of the royalty-free BA22 family, this processor core is extremely competitive in terms of high performance and low power consumption and has best-in-class code density.
    Block Diagram -- 32-bit Basic Application Processor
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