XSPI PHY IP
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xSPI Flash Memory Controller
- Compatible to most SPI protocols used by the NOR-Flash vendors including xSPI (JEDEC’s JESD251), and Xccela
- Single, Dual, Quad, Twin-Quad and Octal SPI lanes. Single and Dual Transfer Rate (STR and DTR)
- Programmable bit-length and number of SPI lanes used for command, address, latency (dummy cycle) and data. Programmable command encoding
- XIP - Allows AHB bus masters to read directly from the flash with zero software overhead.
