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XSPI PHY IP

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Compare 3 IP from 3 vendors (1 - 3)
  • Host controller IP for controlling flash and other devices on the SPI bus: Quad SPI, Octal SPI, and xSPI
    • Flexibility: Multiple SPI protocol support within single IP
    • Simplicity: PHY-less IoT operation, or soft storage combo PHY IP simplifies SoC timing
    • High Performance: Supports maximum Quad SPI / Octal SPI data rates and XIP (Execute In Place)
  • xSPI, HyperBus™, and Xccela™ Serial Memory Controller
    • The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it.
    • The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards.
    Block Diagram -- xSPI, HyperBus™, and Xccela™ Serial Memory Controller
  • xSPI Multiple Bus Memory Controller
    • SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.
    • JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.
    Block Diagram -- xSPI Multiple Bus Memory Controller
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