VeriSilicon IP
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Microprocessor IP for video codecs and video processing -- High Number of Streams Decoder For Data Center
- Enables up to 256 streams decoding with robustness, high throughput single-core solution, or multi-core solution, supporting VVC, AV1, HEVC, H.264, AVS3, AVS2, VP9 video formats, JPEG, and legacy formats.
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Microprocessor IP for video codecs and video processing -- High Number of Streams Encoder For Data Center
- Enables up to 256 streams encoding with high video quality single-core solution, or multi-core solution, supporting AV1, HEVC, H.264, VP9 video formats and JPEG.
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SMIC 0.13um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
- SMIC 0.13um Logic 1P8M 1.2V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power
- Engineered for Synthesizability and Routability
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256 8-bit-MAC DSP core
- High performance vector signal processing and efficient control code processing
- 256 8-bit macs, or 128 16-bit macs, or 32-bit macs per cycle
- Flexible vector permute operations
- Maskable vector lanes
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32 8-bit-MAC Vector DSP Core
- High performance vector signal processing and efficient control code processing
- 32 8-bit macs, or 16 16-bit macs, or 8 32-bit macs per cycle
- Flexible vector permute operations
- Maskable vector lanes
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128 8-bit-MAC Vector DSP Core
- High performance vector signal processing and efficient control code processing
- 256 8-bit macs, or 128 16-bit macs, or 32-bit macs per cycle
- Flexible vector permute operations
- Maskable vector lanes
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Quad MAC DSP core
- Four 16b macs/cycle or Two 32b macs/cycle
- 8/16/32/64 data types
- SIMD support
- High precision (upto 72 bit accumulation)
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2D GPU IP Core - Target Display Resolution: 8K
- Xwindow (EXA)
- Hardware Composer (HWC)
- DirectFB
- Pixel Rate (Pixels/Cycle): 4
- Target Display Resolution: 8K
- Direct 3D Tile Status and Buffer Option: yes
- Formats Support: RGB & YUV FP16/32
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2D GPU IP Core - Target Display Resolution: 4K
- Xwindow (EXA)
- Hardware Composer (HWC)
- DirectFB
- Pixel Rate (Pixels/Cycle): 2
- Target Display Resolution: 4K
- Direct 3D Tile Status and Buffer Option: yes
- Formats Support: RGB & YUV FP16/32
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2D GPU IP Core - Target Display Resolution: 2.5K~4K
- Xwindow (EXA)
- Hardware Composer (HWC)
- DirectFB
- Pixel Rate (Pixels/Cycle): 4
- Target Display Resolution: 2.5K~4K
- Direct 3D Tile Status and Buffer Option: yes
- Formats Support: RGB & YUV Limited