VESA Display Stream Compression IP
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26
IP
from 9 vendors
(1
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10)
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VESA Display Stream Compression (DSC) IP Core
- Supports Versions 1.1, 1.2 and 1.2a
- Supports RGB and YCbCr color spaces
- 1-to-8 slice support
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
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VESA DSC Encoder IP
- Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
- Full DSC Encoder functionality.
- Supports below coding schemes,
- Supports RGB/YCbCr 4:4:4, YCbCr 4:2:2 simple, YCbCr 4:2:2 native and YCbCr 4:2:0 native coding.
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VESA DSC Decoder IP
- Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
- Full DSC Encoder functionality.
- Supports below coding schemes,
- Supports RGB/YCbCr 4:4:4, YCbCr 4:2:2 simple, YCbCr 4:2:2 native and YCbCr 4:2:0 native coding.
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Scalable Ultra-High Throughput DSC 1.2b Decoder
- VESA DSC 1.2b Compliant, Complete and Standalone Operation
- Trouble-Free Technology Map and Implementation
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Scalable Ultra-High Throughput DSC 1.2b Encoder
- Full compliance with the VESA DSC 1.2b specification
- Backwards compatible with VESA DSC 1.1
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DSC 1.2b Decoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
- Supports all DSC 1.2b mandatory and optional coding schemes
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DSC 1.2b Encoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
- Supports all DSC 1.2b mandatory and optional coding schemes
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VDC-M Encoder IP
- Supports VDC-M specification version 1.1 and 1.2.
- Supports full VDC-M encoder functionality.
- Supports following maximum bitrates (BPPmax), as follows:
- Supports any integer slice per line values