VESA DSC Decoder IP
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16
IP
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VESA DSC Decoder IP
- Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
- Full DSC Encoder functionality.
- Supports below coding schemes,
- Supports RGB/YCbCr 4:4:4, YCbCr 4:2:2 simple, YCbCr 4:2:2 native and YCbCr 4:2:0 native coding.
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VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
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VESA DSC V1.2 Decoder
- • Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
- • Low gate count and low latency implementation
- • Three clock domains
- • Stream and APB clocks operate the applicable interfaces
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Scalable Ultra-High Throughput DSC 1.2b Decoder
- VESA DSC 1.2b Compliant, Complete and Standalone Operation
- Trouble-Free Technology Map and Implementation
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VESA DSC (Display Stream Compression) 1.2b Video Decoder
- VESA DSC 1.2 compliant
- Supports all DSC 1.2 mandatory encoding mechanisms
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MIPI DSI-2 with VESA DSC
- Fully compliant to MIPI and VESA standards
- Small footprint
- Code validated with HAL and 0-in-CDC
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Display Stream Compression (DSC 1.2) Decoder
- VESA DSC 1.2 Compliant
- Capable of decoding 4K video at 30fps in FPGA and ASIC
- Decode 8K video at 30fps in ASIC applications
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VESA DSC V1.2 Encoder
- Fully compliant to VESA standards
- Small footprint
- Code validated with HAL and 0-in-CDC
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DSC 1.2b Decoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
- Supports all DSC 1.2b mandatory and optional coding schemes
