Vesa dsc decoder IP

Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications.

Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.

The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standard.
It supports decoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits per component color depths.
The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.

VESA introduced the first Display Stream Compression (DSC) standard in 2014. The DSC 1.1 has been incorporated into the VESA Embedded DisplayPort (eDP) and MIPI® DSI embedded mobile interface standards. The latest VESA Display Compression-M (VDC-M) standard has also been adopted into the MIPI DSI standard. For mobile applications, DSC 1.1 and VDC-M mainly serve to reduce the video interface data rate, which reduces system power, prolongs battery life, and reduces interconnects to enable sleeker designs. For external display interfaces, DSC 1.2b extends resolution across existing connectors and cables, enabling 8K video and legacy support from the same connection.
Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB. It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
Programmable display resolutions

Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.

VESA DSC Decoder IP