Vesa dsc IP

Compare 53 IP from 13 vendors (1 - 10)

VESA DSC Encoder IIP
- Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
- Full DSC Encoder functionality.
- Supports below coding schemes,
- Modified Median-Adaptive Prediction (MMAP)
VESA DSC Decoder IIP
- Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
- Full DSC Decoder functionality.
- Supports below coding schemes,
- Modified Median-Adaptive Prediction (MMAP)
VESA DSC 1.2a Encoder
- Compliant with the VESA DSC 1.2a and 1.1 specifications
- Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
- Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
- Configurable IP delivers low-power and small area
VESA DSC 1.2a Decoder
- Compliant with the VESA DSC 1.2a and 1.1 specifications
- Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
- Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
- Configurable IP delivers low-power and small area
AC VESA DSC 1.2a Encoder
- Compliant with the VESA DSC 1.2a and 1.1 specifications
- Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
- Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
- Configurable IP delivers low-power and small area
VESA DSC Encoder and Decoder IP Solutions
MIPI DSI-2 with VESA DSC
- Fully compliant to MIPI and VESA standards
- Small footprint
- Code validated with HAL and 0-in-CDC
VESA DSC V1.2 Decoder
- • Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
- • Low gate count and low latency implementation
- • Three clock domains
- • Stream and APB clocks operate the applicable interfaces
VESA DSC V1.2 Encoder
- Fully compliant to VESA standards
- Small footprint
- Code validated with HAL and 0-in-CDC
Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
- The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standard.
- It supports decoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits per component color depths.
- The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.

VESA DSC IP