UltraScale IP
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104
IP
from 24 vendors
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10)
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Zynq UltraScale+ RFSoC RF Data Converter
- Up to 16 14-bit 6.554 GSPS RF-DACs
- Eight 12-bit 4.096 GSPS RF-ADCs, or 16 12-bit 2.058 GSPS RF-ADCs, depending on the device
- Supports phase alignment between multiple converters channels on a single or multiple devices
- Pre-programs RF-DAC and RF-ADC with key user-defined parameters
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Zynq UltraScale+ MPSoC Processing System IP
- Enable/Disable I/O Peripherals (IOP)
- Enable/Disable AXI I/O ports (AIO)
- MIO Configuration
- Extended MULTIPLE USE I/Os (EMIO)
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UltraScale+ Device Integrated Block for PCI Express (PCIe)
- Designed to PCI Express Base Specification 3.1
- PCI Express Endpoint, Legacy Endpoint or Root Port Port Modes
- x1, x2, x4, x8 or x16 link widths
- Gen1, Gen2 and Gen3 link speeds
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UltraScale Integrated 100G Ethernet Subsystem
- Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
- No charge 100G Ethernet MAC and PCS license key enabled
- Optional fee based soft 100G RS-FEC for UltraScale FPGAs
- 1588 1-step and 2-step hardware time stamping
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UltraScale / UltraScale+ Interlaken
- The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
- The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
- The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
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UltraScale Interlaken
- The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
- The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
- The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.
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UltraScale Integrated 100G Ethernet MAC/PCS
- Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
- No charge license key enabled
- 1588 1-step and 2-step hardware time stamping
- Allows insertion of custom logic such as RS-FEC between the 100G Ethernet integrated block and GT
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UltraScale Gen3 Integrated Block for PCI Express (PCIe)
- High Peformance and High Bandwidth Applications
- Compute and Data Co-processing Applications
- Medical Imaging, High-Performance Computing & Communications Packet Processing
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UltraScale FPGAs Transceivers Wizard
- Creates customized protocol presets to configure high-speed serial transceivers in UltraScale FPGAs
- Protocol presets provided for 10GBASE-R, 10GBASE-KR, 3G-SDI, Aurora 8B/10B, Aurora 64B/66B, CAUI-4, CAUI-10, CEI-11G, CPRI™, Gigabit Ethernet, HD-SDI, HMC, Interlaken, JESD204B, MoSys Bandwidth Engine, OTL 4.10, OTU2/2e, OTU4, QSGMII, RXAUI, SATA, Serial RapidIO Gen2, XAUI, XLAUI, and DisplayPort.