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USB-C 3.1 IP

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Compare 57 IP from 3 vendors (1 - 10)
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5A 1.2V, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5A 1.2V, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 7FF x1, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 7FF x1, North/South Poly Orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 6FF x1, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 6FF x1, North/South Poly Orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 16FFC, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 16FFC, North/South Poly Orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 12FFC, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 12FFC, North/South Poly Orientation
  • USB-C 3.1 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.3 Tx PHYs, USB-C 3.1/DisplayPort 1.3 Tx controllers with HDCP 2.2 and HDCP 1.4 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
    • Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.3 Tx supporting RBR, HBR1, HBR2 and HBR3 bitrates
    • Controllers support Device, Host, and Dual-Role Device USB-C 3.1 as well as DisplayPort 1.3 Tx with HDCP 2.2 content protection
    Block Diagram -- USB-C 3.1 DP/TX PHY ebdaux for TSMC N5, North/South poly orientation
  • USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
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