IP Catalog > USB 3.2 OTG Controller And PHY

USB 3.2 OTG Controller and PHY IP

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  • Simulation VIP for USB
    • Configurations
    • Gen2x2, Gen1x2, Gen2x1, and Gen1x1
    • Supported DUT Models
    • Host, Device and PHY Model for USB2 or USB3
  • USB 3.0/3.1/3.2/SSIC Verification IP
    • Compliant with USB 3.0/3.1/3.2 specification version 1.0
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1 , USB 3.2 and 3.0 OTG
    • Complete solution for thorough chip-level verification
    • Comprehensive model support a Host, Device, Hub, PHY
    Block Diagram -- USB 3.0/3.1/3.2/SSIC Verification IP
  • MIPI GbD USB Verification IP
    • Compliant with MIPI Giga bit debug specification version 1.0/1.1
    • Supports the network adaptor for USB
    • Supports the trace applications
    • Supports the Sneak peak applications
    Block Diagram -- MIPI GbD USB Verification IP
  • USB3.x HOST IIP
    • USB 3.0/3.1/3.2 Common support
    • Compliant with USB 3.0/3.1/3.2 specification
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG
    • Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
    Block Diagram -- USB3.x HOST IIP
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Semiconductor IP