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UFS Device Controller IP

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Search (58)
Compare 58 IP from 7 vendors (1 - 10)
  • UFS 2.1 Device Controller IP
    • The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.
    • The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.
    Block Diagram -- UFS 2.1 Device Controller IP
  • MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro
    • Compliant with UFS Specification v3.1 and backward compatible to UFS v3.0 & v2.1
    • AXI support
    • All UPIU processing
    • Data-in, data-out, command, response, RTT, query, task management and reject
    Block Diagram -- MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro
  • UFS Controller - Verifies compliance and performance of UFS interfaces in SoCs
    • The UFS Controller Verification IP (VIP) ensures proper operation and compliance of UFS interfaces in SoC designs. It supports UFS 2.0, 2.1, 3.0, and 3.1 standards, enabling efficient validation of high-speed data transfers and power management.
    • The VIP is critical for validating UFS controllers in a wide range of applications, from AI/ML systems to mobile devices and automotive infotainment. It ensures optimal performance, reliability, and seamless integration in diverse environments
    Block Diagram -- UFS Controller - Verifies compliance and performance of UFS interfaces in SoCs
  • UFSHCI 3.0 - UFS Host Controller Interface
    • Compliant with JEDEC UFSHCI Standard version 3.0 specification
    • Compliant with JEDEC UFS Standard version 3.0 specification
    • Up to 32 doorbells for UTP transfer
    • 4 sets of multi RTTs
    Block Diagram -- UFSHCI 3.0 - UFS Host Controller Interface
  • UFSHCI 4.0 - UFS Host Controller Interface
    • Compliant with JEDEC UFSHCI Standard version 4.0 specification
    • Compliant with JEDEC UFS Standard version 4.0 specification
    • Up to 32 doorbells for UTP transfers
    • Up to 32 Multi-Circular Queue (MCQ) UTP transfer requests
    Block Diagram -- UFSHCI 4.0 - UFS Host Controller Interface
  • UFS 2.1 Host Controller IP
    • JEDEC UFS 2.0 and UFS HCI 2.0 Compliant
    • Supports high performance M-PHY v3.0 type-1
    • 2 lanes @ 5.9 Gbps per lane
    • UniPro v1.6 link layer
    • Definable write-protect group size
    Block Diagram -- UFS 2.1 Host Controller IP
  • UFS HOST Controller IIP
    • Supports high performance M-PHY type-1.
    • Supports full UFS Host functionality.
    • Supports UFS driver layer over UniPro.
    • Supports configurable cport.
    Block Diagram -- UFS HOST Controller IIP
  • UFS 3.0 Host Controller
    • Compliant with the JEDEC UFS, UFSHCI v4.0 and UFS card v1.1 standards
    • Enables data and privacy protection using Inline Encryption (AES-XTS) and RPMB
    • Delivered as UFS host application layer integrated with Synopsys MIPI UniPro v2.0 Controller IP
    • Manages UFS protocol between host and external UFS device
    Block Diagram -- UFS 3.0 Host Controller
  • MIPI UFS v2.1 Host Controller IP, Compatible with M-PHY and Unipro
    • Compliant with UFS Specification v2.1 and backward compatible t
    • AXI support
    • All UPIU processing
    • Data-in, data-out, command, response, RTT, query, task management and reject
    Block Diagram -- MIPI UFS v2.1 Host Controller IP, Compatible with M-PHY and Unipro
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