TCP Offload Engine IP
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16
IP
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1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
- INT 1011 is the only SOC IP Core that implements a full 1G bit TCP Stack in Handcrafted, Ultra Low Latency and Very High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation.
- INT 2011 is the only SOC that integrates 1G TOE + 1 GEMAC + Host interfaces in the smallest logic footprint. It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications.
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10 G bit TCP Offload Engine + PCIe/DMA SOC IP
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
- Fourth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and TCP protocol proven.
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1G TCP Offload Engine TOE Very Low Latency (TOE)
- Ideal for high performance and mid performance specialized, differentiable ASICs or FPGAs for Network security or Network infrastructure applications
- Less than 4000 Xilinx slices, Altera ALMs or 150,000 ASIC gates + on-chip memory
- Fully integrated 100 M bit/1-G bit high performance EMAC.
- Scalable MAC Rx FIFOs and Tx FIFOs make it ideal for optimizing system performance.
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1G TCP Offload Engine TOE +PCIe Very Low Latency (TOE+PCIe)
- INT 1012 is the only SOC that integrates 1G TOE + 1 GEMAC + PCIe/DMA + Host interfaces in the smallest logic footprint.
- It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications.
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100G bps Full TCP & UDP Offload Engine
- Increase your TCP and UDP Network actual performance by up to 600%
- Built around Proven and Mature TCP and UDP technology since 2009.
- 40G: In production. Performed Live demo of 40G at Super Computing 2015
- Qualified on Altera/Intel and Xilinx. FPGA Subsystems Solutions available now
- First company to implement and deliver Full TCP Stack in High performance FPGA in 2009.
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40G-1K Sess. TCP + UDP Offload Engine
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
- Eighth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
- All stages of Full TCP stack implemented in High performance hardware
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25G-1K Sess. TCP + UDP Offload Engine
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera
- FPGAs or Structured/ASIC flow.
- Eighth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
- All stages of Full TCP stack implemented in High performance hardware
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10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
- Seventh Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
- All stages of Full TCP stack implemented in High performance hardware
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10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE)
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
- Fifth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
- All stages of Full TCP stack implemented in High performance hardware
