INT 40011 is the only SOC IP Core that implements a full 40G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation. It provides the lowest latency and highest performance in the industry. No exceptions…..
INT 40011 is the only SOC that integrates 40G TOE + 40 GEMAC(opt) + Host interfaces in the smallest logic footprint. It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications. It is recommended for use in, among others, high performance Cloud Servers, security appliances, Web Servers, Application servers, NICs, SAN/NAS and data center equipment design applications. It provides key IP building blocks for very high performance 40-Giga bit Ethernet ASIC/ASSP/FPGAs.
INT 40011 has built in advanced architectural flexibility that provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others and customize them for their specific design application.
INT 40011 can process TCP/IP sessions as client/server in mixed session mode for Network equipment and in-line network security appliances, simultaneously, at 40/25-G-bit rate. This relieves the host CPU from costly TCP/IP software related session setup/tear down, data copying and maintenance tasks thereby delivering 10x to 20x TCP/IP network performance improvement when compared with TCP/IP software.
INT 40011 also implements IGMP V1/V1/V3 protocol processing in hardware across all sessions. Available as an option to save BRAM and logic resources.
40G-1K Sess. TCP + UDP Offload Engine
Overview
Key Features
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
- Eighth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
- All stages of Full TCP stack implemented in High performance hardware
- Ultra-Low Latency through 40 G TOE around 130+ ns
- Native 40G Architecture running at full 40G Network line rate
- Ultra-High Throughput: Receives and Sends sustained large TCP payloads, depending upon remote server/client’s capability.
- Fully Integrated and tested on Altera/Xilinx FPGAs; TOE+Host_I/F SoC IP bundle
Block Diagram
