Still Image Encoder IP
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23
IP
from 8 vendors
(1
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10)
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10/12-bit Extended & 8-bit Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control
- Complete, Compliant and Standalone Operation
- Extra Capabilities
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Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control
- Complete, Compliant and Standalone Operation
- Extra Capabilities
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JPEG Encoder FPGA Core
- JPEG Compliance (ISO/IEC 10918-1) High-accuracy and high-speed DCT core options Fixed entropy table, sixteen programmable quantization tables (8 Chroma, 8 Luna) Supports all possible scan configurations and all JPEG formats for input and output data (up to 8 color components) Any image size up to 16K x 16K 1 clock/pixel greyscale, 1.5 clock/pixel YUV 4:2:0, 2 clock/pixel YUV 4:2:2 Custom versions available
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JPEG 2000 Encoder - Up to 16-bit per Component Lossy & Numerically Lossless Image & Video Compression
- ISO/IEC 15444-1 JPEG 2000 Image Coding System Compliance
- Programmable JPEG 2000 Encoding Options
- Smooth System Integration
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Motion JPEG Encoder
- Supports Xilinx® Zynq®-7000 AP SoC and 7 series FPGA families
- Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
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Up To 5 MPixel Multi-Format Encoder
- State of the art video encoding quality
- Unique multi-format and scalable architecture
- Scalable video resolution up to 8K resolution, support for multi-stream encoding
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Lossless MJPEG Encoder
- Plug-and-Play IP core with Xilinx implementation tools (Vivado)
- Free reference designs available for AMD-Xilinx ZCU102 on request
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H 265 Video Encoder IP
- All-hardware Design (without embedded processors)
- • High Speed (Low latency)
- • Small Silicon Footprint
- • Low Power
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Lossless MJPEG Decoder
- Plug-and-Play IP core with Xilinx implementation tools (Vivado)
- Free reference designs available for AMD-Xilinx ZCU102 on request
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AV1/HEVC/AVC Single-core Encoder Video IP
- Frame buffer compression (FBC)
- Low delay encoding
- Configurable IP
