Still Image Decoder IP

• Baseline & Extended ISO/IEC 10918-1 JPEG Compliance
• Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard
• Additional Processing Capabilities

• Complete, Compliant and Standalone Operation
• Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard
• Ease of Integration

• Supports Xilinx® Zynq®-7000 AP SoC and 7 series FPGA families
• Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard

• Plug-and-Play IP core with Xilinx implementation tools (Vivado)
• Free reference designs available for AMD-Xilinx ZCU102 on request

• Support Video and Still Image Decoding formats:
• •H.264 Baseline, Main and High Profiles, levels 1 – 5.1
• •H.264 SVC Scalable Baseline and High Profiles, Base Layer only
• •H.264 MVC Stereo High Profile

• Plug-and-Play IP core with Xilinx implementation tools (Vivado)
• Free reference designs available for AMD-Xilinx ZCU102 on request

• The arithmetic accuracy satisfies the requirement of compliance testing of JPEG Part2 (ISO/IEC10918-2).
• Image Data I/O Format:Block Interleaved Format.
• Image Size:Any size that can be divided by MCU unit.
• Quantization table / Huffman table:Written from external during compression, and downloaded from compressed data during decompression.

• ?Based on JPEG Baseline process Standards.
• ?The arithmetic accuracy also satisfies the requirement of compliance testing of JPEG Part2 ?ISO/IEC10918-2?j.
• ?Image Data Output Format:Block Interleaved Format
• ?Image Size:Any size that can be divided by MCU unit.

• 96fps@100MHz
• 16Sample/clk
• ISO/IEC 10918-1, ITU-T T.81

Enables up to 256 streams decoding with robustness, high throughput single-core solution, or multi-core solution, supporting VVC, AV1, HEVC, H.264, AVS3, AVS2, VP9 video formats, JPEG, and legacy formats.