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Still Image Decoder IP

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Compare 11 IP from 6 vendors (1 - 10)
  • Microprocessor IP for video codecs and video processing -- High Number of Streams Decoder For Data Center
    • Enables up to 256 streams decoding with robustness, high throughput single-core solution, or multi-core solution, supporting VVC, AV1, HEVC, H.264, AVS3, AVS2, VP9 video formats, JPEG, and legacy formats.
    Block Diagram -- Microprocessor IP for video codecs and video processing -- High Number of Streams Decoder For Data Center
  • Lossless MJPEG Decoder
    • Plug-and-Play IP core with Xilinx implementation tools (Vivado)
    • Free reference designs available for AMD-Xilinx ZCU102 on request
    Block Diagram -- Lossless MJPEG Decoder
  • JPEG Decoder 1-pixel/clock
    • - Image Format: Frame sequential method
    • - Input/Output Format: YUV 4:4:4/4:2:2/4:2:0/4:0:0
    • - Data bus protcol: AXI
    • - CPU bus protcol: AHB
  • Multi-format video decoder IP Core
    • Multi-format video decoder supporting all significant video standards and proprietary video formats.
    • First HW IP decoder to support VP8 for Google’s WebM and WebRTC. 
    Block Diagram -- Multi-format video decoder IP Core
  • JPEG Decoder Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
    • The arithmetic accuracy satisfies the requirement of compliance testing of JPEG Part2 (ISO/IEC10918-2).
    • Image Data I/O Format:Block Interleaved Format.
    • Image Size:Any size that can be divided by MCU unit.
    • Quantization table / Huffman table:Written from external during compression, and downloaded from compressed data during decompression.
    Block Diagram -- JPEG Decoder Full HD(YUV422) 30fps@63MHz. (2Sample/clk)
  • Multi-Channel MJPEG Decoder
    • Supports Xilinx® Zynq®-7000 AP SoC and 7 series FPGA families
    • Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
  • JPEG Decoder 8K(YUV422) 48fps@200MHz, (16Sample/clk)
    • 96fps@100MHz
    • 16Sample/clk
    • ISO/IEC 10918-1, ITU-T T.81
    Block Diagram -- JPEG Decoder 8K(YUV422) 48fps@200MHz, (16Sample/clk)
  • 8/10/12-bit Extended JPEG Decoder
    • Baseline & Extended ISO/IEC 10918-1 JPEG Compliance
    • Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard
    • Additional Processing Capabilities
    Block Diagram -- 8/10/12-bit Extended JPEG Decoder
  • 8-bit Baseline JPEG Decoder
    • The JPEG-D core is a standalone and high-performance 8-bit Baseline JPEG decoder for still image and video compression applications.
    • Compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes this IP core suitable for interoperable systems and devices.
    • The JPEG-D is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
    Block Diagram -- 8-bit Baseline JPEG Decoder
  • Lossless MJPEG Encoder
    • Plug-and-Play IP core with Xilinx implementation tools (Vivado)
    • Free reference designs available for AMD-Xilinx ZCU102 on request
    Block Diagram -- Lossless MJPEG Encoder
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