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Serial RapidIO IP

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Compare 18 IP from 9 vendors (1 - 10)
  • Serial RapidIO 2.1 Endpoint IP Core
    • LatticeECP3 AMC Evaluation board
    • Associated cables
    • AMC interface card
    • Demonstration bitstreams and files
    Block Diagram -- Serial RapidIO 2.1 Endpoint IP Core
  • Serial RapidIO - Physical Layer Interface
    • Supports High Speed 1x Mode (up to 2.5 Gbps)
    • 8B/10B Encoding and Decoding
    • Clock and Data Recovery (CDR)
    • Lane Synchronization
    Block Diagram -- Serial RapidIO - Physical Layer Interface
  • LogiCORE IP Serial RapidIO Gen 2
    • 1x, 2x, & 4x Serial PHY - supports Artix-7, Kintex-7, Zynq-7000, Virtex-7, and Virtex-6 FPGAs
    • 1x, 2x & 4x Serial PHY - supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gbps line speed
    • Supports IDLE1 and IDLE2 sequence
    • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Serial RapidIO LogiCORE IP
    • 1x & 4x Serial PHY - Supports Virtex-6 LXT/SXT/HXT, Spartan-6 LXT, Virtex-5 LXT/SXT/FXT, and Virtex-4 FX FPGAs
    • 1x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0 Gpbs line speed
    • 1x & 4x Serial PHY - 64-bit internal data path
    • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Serial RapidIO Controller
    • Fully compliant with the RapidIO specification revision 2.2,
    • Simple transaction interface with Host processor and DMA Engine,
    • Configurable FIFOs implemented by BlockRAM in both transmit and receive paths,
    • Register file containing all necessary architectural registers providing total software control of IP core,
  • UltraScale FPGAs Transceivers Wizard
    • Creates customized protocol presets to configure high-speed serial transceivers in UltraScale FPGAs
    • Protocol presets provided for 10GBASE-R, 10GBASE-KR, 3G-SDI, Aurora 8B/10B, Aurora 64B/66B, CAUI-4, CAUI-10, CEI-11G, CPRI™, Gigabit Ethernet, HD-SDI, HMC, Interlaken, JESD204B, MoSys Bandwidth Engine, OTL 4.10, OTU2/2e, OTU4, QSGMII, RXAUI, SATA, Serial RapidIO Gen2, XAUI, XLAUI, and DisplayPort.
  • Virtex-5 FPGA RocketIO GTX Transceiver Wizard
    • Creates customized HDL wrappers to configure high-speed serial transceivers
    • Predefined protocol templates support Aurora (8B/10B and 64B/66B), CPRI™, Fibre Channel 1x, Gigabit Ethernet, HD-SDI, OBSAI, OC3, OC12, OC48, PCI EXPRESS® (PCIe®) Generation I and II, SATA 1.5 Gbps, SATA 3 Gbps, Serial RapidIO, and XAUI
    • Automatically configures analog settings
  • Virtex-5 FPGA RocketIO GTP Transceiver Wizard
    • Creates customized HDL wrappers to configure high-speed serial transceivers
    • Predefined protocol templates support Aurora 8B/10B, CPRI™, Fibre Channel 1x, Gigabit Ethernet, HD-SDI, OBSAI, OC3, OC12, OC48, PCI Express® (PCIe®) generation1, SATA 1.5 Gbps, SATA 3 Gbps, Serial RapidIO, and XAUI
    • Automatically configures analog settings
  • RapidIO 2.0 PHY & Controller
    • One to Four independent 1.25/2.5/3.125Gbps per ports
    • Features as per RapidIO Specification revision v2.2
    • Precision low jitter master PLL and CDR loop
    • Supporting a 10 bit SerDes interface
  • RapidIO EndPoint Controller IP
    • Compliant with RapidIO Interconnect 2.2 specification
    • Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
    • Supports high link utilization and low latency
    • Supports efficient receive and transmit buffering scheme
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