Samsung Foundry 14LPP IP

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Compare 17 IP from 5 vendors (1 - 10)
  • HSSTP TX PHY 5nm Samsung Foundry
    • Samsung Foundry 5nm (SF5A) CMOS device technology
    • 1.8V±5%, 0.75V±5% power supply
    • Fully supports ARM HSSTP v6.0
    • Supports 1.5/3/6Gbps data rates
    Block Diagram -- HSSTP TX PHY 5nm Samsung Foundry
  • eFPGA IP and FPGA Software Built on Samsung Foundry 28nm FDSOI
    • Homogenous Fabric architecture
    • Super Logic Cell (SLC) consisting of 8 LUT4, 8 registers
  • Digital Cell Library Samsung
    • Compact standard cell library targeting a wide range of foundries and processes
    • Customised for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
    • Power Management library for low-power designs
    • Timing models for customisable range of PVT
    Block Diagram -- Digital Cell Library Samsung
  • PVT Sensor Subsystem
    • Start-up time: Typ 20us
    • Current consumption: Max 25uA
    • Industry standard digital interface
    Block Diagram -- PVT Sensor Subsystem
  • Sleep Management Subsystem
    • Power-On-Reset
    • Programmable relaxation oscillator
    • Low Power Comparator
    Block Diagram -- Sleep Management Subsystem
  • Power Management Subsystem
    • Start-up time: Typ 20us
    • Industry standard digital interface
    • Configurable logic to control sequencing and monitoring
    Block Diagram -- Power Management Subsystem
  • Sensor Interface Subsystem
    • Industry standard digital interface
    • Fully integrated macro
    • Standard AMBA APB interface
    Block Diagram -- Sensor Interface Subsystem
  • Digital Cell Library SMIC
    • Compact standard cell library targeting a wide range of foundries and processes
    • Customized for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
    • Power Management library for low-power designs
    • Timing models for customizable range of PVT
    Block Diagram -- Digital Cell Library SMIC
  • Digital Cell Library UMC
    • Compact standard cell library targeting a wide range of foundries and processes
    • Customized for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
    • Power Management library for low-power designs
    • Timing models for customizable range of PVT
    Block Diagram -- Digital Cell Library UMC
  • Digital Cell Library TSMC
    • Compact standard cell library targeting a wide range of foundries and processes
    Block Diagram -- Digital Cell Library TSMC
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Semiconductor IP