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SD Card UHS-II PHY IP

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  • Simulation VIP for SD CARD and SDIO
    • SD Card device standard
    • Speed Range A and B
    • Default Speed Range A and faster Range B support
    • PHY-LINK I/F
  • SD UHS2 PHY & Controller
    • DTI SD host controller facilitates host equipment to communicate with SD card.
    • It supports both legacy and ultra-high speed II (UHS-II) interfaces.
  • SD Card Input/Output Protocol Controller
    • Compliance with Embedded MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
    • Full compatibility with previous versions of MultiMediaCards (backward compatibility)
    • Full compliance with SD memory card specifications version 4.2 ( SPI mode and UHS-II mode not supported)
  • SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
    • The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies.
    • SD 4.1 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
  • SD 4.1 Device Controller IP
    • Fully compliant core with proven silicon
    • Compliant with SD Specification Part E SD Specification 4.0
    • Transfers up to 300 MB/s (UHS156)
    • Supports Asynchronous Interrupt to Host controller
    • Enhanced power management using new Power
    Block Diagram -- SD 4.1 Device Controller IP
  • SD 4.1 eMMC 5.1 Dual Host Controller IP
    • The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
    • The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
    • eMMC 5.1 is backward compatible to the previous versions.
    •  
    Block Diagram -- SD 4.1 eMMC 5.1 Dual Host Controller IP
  • SD 4.1 Hardware Validation Platform
    • Designed to be cost-effective and Linux based, this SD 4.1 hardware validation platform (HVP) consists of Arasan’s SD4.0 IP mapped into FPGA’s, offering full speed physical connectivity to a complementary SoC host or memory card device.
    Block Diagram -- SD 4.1 Hardware Validation Platform
  • SDIO UHS II Verification IP
    • Supports SD specification UHS-II Adddendum version 2.00 compliant.
    • Supports Part E1 SDIO specification version 4.10.
    • Supports SD specification physical layer version 4.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft).
    • Supports bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes.
    Block Diagram -- SDIO UHS II Verification IP
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