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SAR ADC IP

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Compare 187 IP from 47 vendors (1 - 10)
  • SAR ADC
    • High Sampling Rate: Capable of sampling up to 640 million samples per second, making it suitable for ultra-high-speed applications
    • 12-bit Resolution: Delivers 12-bit digital output, providing superior precision and accuracy in signal quantization
    • SAR Architecture: Ensures high speed and low latency with excellent power efficiency
    • Ultra-Low Power Consumption: Optimized for minimal power usage, ideal for energy-sensitive applications
    Block Diagram -- SAR ADC
  • 10/12-bit SAR ADC
    • The SAR ADC IP is a small-size, low power analog to digital converter which leverages charge-redistribution successive approximation technology
    • It offers a reliable solution of analog-to-digital signal conversion for general application
    • Innosilicon SAR ADC IP consists of input MUX, ADC core, and digital logic
    Block Diagram -- 10/12-bit SAR ADC
  • 10-Bit SAR ADC 5MSPS
    •  Fully Differential Mode: -0.6V–0.6V
    •  Pseudo Differential Mode: 0V-1.2V
    •  1.8V Analog/1.0V Digital
    •  Resolution: 10-bit
    Block Diagram -- 10-Bit SAR ADC 5MSPS
  • 10bit 1Msps SAR ADC IP Core
    • 10-bit Parallel Output.
    • Conversion time/Sampling frequency = 1 us/ 1Msps
    • CLOCK REQUIREMENT: 2 MHz- 20 MHz
    Block Diagram -- 10bit 1Msps SAR ADC IP Core
  • 12-bit, 2MS/s SAR ADC IP for Microcontroller Business in TSMC 55nm
    • 12-bit SAR ADC @ 2MS/s conversion range, working up-to 4MS/s.
    • Integrated PGA selectable with multiplexer.
    • The ADC power scales linearly with clock speed. (DC to 2Msps)
    • Zero DC power
  • Low-power, high-speed 11-bit, 8 GSPS SAR ADC - TSMC 28nm HPC+
    • 11-bit Resolution
    • 8 GSPS Sampling Rate
    • 264 mW Power Consumption
  • 12-bit 1-channel up to 1 MSPS low power SAR ADC
    • Global Foundries Embedded EEPROM 55nm
    • INL ±3LSB
    • DNL ±1LSB
    • SINAD 65dB@1MSPS
    Block Diagram -- 12-bit 1-channel up to 1 MSPS low power SAR ADC
  • 12-bit 1-channel up to 1.25MSPS SAR ADC
    • TSMC eFlash 28nm technology
    • INL ±3LSB
    • DNL ±1LSB
    • SINAD 64dB@5V (1.25MSPS)
    Block Diagram -- 12-bit 1-channel up to 1.25MSPS SAR ADC
  • 11-bit SAR ADC - TSMC 28nm HPC+
    • The A11B4G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
    • It is a hybrid successive approximation register (SAR) ADC, with a 11-bit resolution, and a sampling speed of 4 gigasamples per second (GSPS).
  • 12-bit 1-channel 5 to 100 kSPS SAR ADC
    • TSMC CMOD 55nm
    • Sample rate from 5kSPS to 100kSPS
    • Resolution 12 bit
    • Buil-in pre-amplifier and low pass filter
    Block Diagram -- 12-bit 1-channel 5 to 100 kSPS SAR ADC
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