RRAM IP
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ReRAM NVM in 130nm CMOS, S130
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Single port SRAM compiler based on Racyics® R188 logic memory cell with dual-well architecture
- Supply voltage 0.55 V to 0.8 V enabled with Racyics® ABB
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Dual-Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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Single Port SRAM Compiler GF22FDX Low Power
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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Single Port SRAM Compiler GlobalFoundries 55LPx Ultra-high density, low power, up to 320K bits
- Capacity to 320K bits
- Word width: 8 to 144 bits
- Address range: 32 to 8k
- Nominal voltage: 1.2V
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USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
- USB 2.0 USB IF high-speed certified (TID# 70680007)
- Supports both High Speed (480 Mbps) and Full Speed (12 Mbps)
- High speed or Full speed operation selection through Software
- ULPI Interface support
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Frame Rate Converter for 4K
- TMC’s FRUC utilizes “MEMC” algorithm optimized by DMNA.
- Extremely small generations of halo, judder, and artifact on the interpolating frames.
- 2:2 pull down and 2:3 pull down detections are implemented.
- Processing functions for motionless section, scrolling ticker, and screen edge are implemented.
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Video Frame Buffer
- Asynchronous video input
- Output video synchronized to the system clock
- Simple user interface looks like a FIFO
- Supports all standard and any custom video resolution
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AVC/H.264 Video Encoder with Compressed Frame Store
- Low power AVC/H.264 encoder
- Small silicon footprint
- Optimized for low-latency
- Low-bit-rate video streaming
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Camera Link Frame Grabber Channel Link Data Processor
- Inclusive of all Camera Link defined camera configurations including the proposed 80 bit extensions which utilize one to three Channel Link or equivalent devices.
- Supports single camera or two independent base cameras for multi-view or 3D stereo applications.
- Fully synchronous pipeline architecture supports high speed implementation in low cost logic devices.
- Dynamic reconfiguration of the processing chain via register interface in addition to a user selected default setup.
