RLDRAM II IP

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RLDRAM II Controller
RLDRAM II Controller with UniPHY
Memory Interface
- Memory Interface generates through a Graphic User Interface the unencrypted Verilog or VHDL design files, UCF constraints, and simulation script files to simplify the memory interface design process.
- Memory modules (DIMM) are supported for DDR3, DDR2 and DDR SDRAMs.
- OS Support
RLDRAM Controller MACO Core
- Controller operates at half the memory clock frequency
- Allows programmable burst lengths of
- Includes a reconfigurable refresh counter
- Command & Write Data pipeline to maximize throughput