RISC-V Automotive CPU IP
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6
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Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- The only Multi-Threaded Out-of-Order RISC-V Core with ASIL-B Certification
- Highly scalable multi-core, multi-cluster, coherent computing solution
- MIPS extensions for improved performance and functionality
- Use in Automotive, Datacenter, and Embedded applications
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32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV32I Base RISC-V ISA
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64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV64I Base RISC-V ISA
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
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Highly scalable inference NPU IP for next-gen AI applications
- ENLIGHT Pro is meticulously engineered to deliver enhanced flexibility, scalability, and configurability, enhancing overall efficiency in a compact footprint.
- ENLIGHT Pro supports the transformer model, a key requirement in modern AI applications, particularly Large Language Models (LLMs). LLMs are instrumental in tasks such as text recognition and generation, trained using deep learning techniques on extensive datasets.
