PCIe to Gen-Z Bridge IP
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Gen-Z Physical Layer for PCIe IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Physical Layer Specification
- Compliant with the Gen-Z 1.1 Physical Layer Abstraction interface
- Multi-lane symmetric link support up to 16 lanes per link
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GENZ VIP
- Supports GENZ Core specification 1.0 and 1.1.
- Supports GENZ Physical layer specification 1.0 and 1.1.
- Supports GENZ Fabric Management specification 1.0.
- Supports Byte-addressable memory access.
