PCI-Express IP
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40
IP
from 13 vendors
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10)
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1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- High speed performance
- Low power architecture
- Robust training
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High Channel Count DMA IP Core for PCI-Express
- Available for Xilinx or Intel (Altera) Devices
- User transmits / receives only user data without PCIe protocol
- AXI standard interfaces for easy integration
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Multi Channel DMA Flex IP Core for PCI-Express
- AXI standard interfaces for easy integration
- User transmits/receives only user data without PCIe protocol
- All AXI Interfaces have adjustable Datawidth and separate clocking
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PCI-Express Device Driver for Windows / Linux
- Open and Close the PCIe Device
- Read and Write Data accesses to the endpoint with 32 or 64-Bit data width
- Write Burst Mode, for sending data to the endpoint with maximum data throughput.
- Memory allocation
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PCI Express - Configurable PCI Express 4.0 IP
- Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
- Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
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Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS)
- Most Likely Sequence Detector(MLSD)
- High speed A/D
- Sub-sampling clock multiplier
- Master Controller
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1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)
- High speed A/D
- Sub-sampling clock multiplier
- Master controller
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General Purpose & Bridge DMA
- DMA-GP Core
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Gigabit Ethernet MAC with AVB
- Fully compliant with IEEE AVB (Audio Video Bridging) Standard
- Full-duplex mode at 10/100/1000 Mbps
- Half-duplex mode at 10/100 Mbps
- Supports IEEE 802.3-2008 compliant MII, RMII, SMII, GMII, RGMII, and SGMII
