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PCI-Express IP

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Compare 37 IP from 13 vendors (1 - 10)
  • 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
    • High speed performance
    • Low power architecture
    • Robust training
    Block Diagram -- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
  • High Channel Count DMA IP Core for PCI-Express
    • Available for Xilinx or Intel (Altera) Devices
    • User transmits / receives only user data without PCIe protocol
    • AXI standard interfaces for easy integration
    Block Diagram -- High Channel Count DMA IP Core for PCI-Express
  • PCI-Express Device Driver for Windows / Linux
    • Open and Close the PCIe Device
    • Read and Write Data accesses to the endpoint with 32 or 64-Bit data width
    • Write Burst Mode, for sending data to the endpoint with maximum data throughput.
    • Memory allocation
  • Multi Channel DMA Flex IP Core for PCI-Express
    • AXI standard interfaces for easy integration
    • User transmits/receives only user data without PCIe protocol
    • All AXI Interfaces have adjustable Datawidth and separate clocking
    Block Diagram -- Multi Channel DMA Flex IP Core for PCI-Express
  • PCI Express - Configurable PCI Express 4.0 IP
    • Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
    • Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
    Block Diagram -- PCI Express - Configurable PCI Express 4.0 IP
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • Programmable Low Power SERDES on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
    • Compact form factor – 0.104 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.8 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN28HPL
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.095 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.6 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 SERDES PHY on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.107 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.9 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
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