High Channel Count DMA IP Core for PCI-Express

Overview

The High Channel Count DMA IP Core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces. This IP addresses continuous streaming applications from up to 64 different datasources. Each channel is able to transmit data into a separate memory area. Up to 16 AXI Stream Masters read DMA Data from the Host and present it to the User Logic. Additional 8 AXI4 Masters are available to interface full AXI or AXI-Lite peripherals with the Host.
The Link Stability detector module measures the signal integrity of the PCI Express Link for lab or production tests to prevent shipments of faulty devices (Xilinx only).
This IP Core enables the developer to build complex PCI Express endpoints with no specific PCI Express Protocol Know How. The user only transmits/receives payload data and does not have to build valid PCI Express packets.

Key Features

Available for Xilinx or Intel (Altera) Devices
User transmits / receives only user data without PCIe protocol
AXI standard interfaces for easy integration
All AXI Interfaces have adjustable Datawidth and separate clocking
Supports linear contiguous Memory as Ringbuffers
Memory Size up to 4 GByte per Streaming Channel
Performance only limited by PCI-Express Bandwidth
Based on Xilinx / Intel integrated PCI-Sig compliant PCIe Block (HIP)
Link Speeds Gen1-3, Link Widths x1-x8
64 Bit or 256-Bit Architecture available

Block Diagram

Deliverables

Encrypted VHDL Source Code for easy Designflow integration
Comprehensive User Guide
Reference Design
Windows / Linux Driver Package (Option)
PCI-Express Testbench with High Speed simulation mode
Technical support

Technical Specifications

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