PCI Express® 5.0 controller IP
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17
IP
from 2 vendors
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10)
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Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)
- Supports all required features of the PCI Express 7.0, 6.x, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
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PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
- High-performance PHY for data center applications
- Low-latency, long-reach, and low-power modes
- Wide range of protocols that support networking, storage, and computing applications
- Multi-protocol support for application flexibility
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Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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Automotive-grade controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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12G Ethernet PHY in Samsung (14nm)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver