PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)

Overview

Key Features

• Supports all required features of the PCI Express 7.0, 6.x, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
• Full Transaction Layer, Data Link Layer and Physical Layer
• Supports up to sixteen 128.0, 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
• Available in 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
• 125 MHz, 250 MHz, 500 MHz, 1 GHz and 2 GHz operation
• Supports PIPE 6.x and PIPE 7.x interface including variable clock and variable data widths up to 128-bit
• Application interfaces include the Synopsys native interface or the optional single- or dual-port 512-bit/1024-bit AXI Bridge supporting Arm AMBA 5/4/3 AXI
• Optional embedded HyperDMA controller with up to 64 read and 64 write channels plus descriptor pre-fetch for high throughput with minimal SoC resource overhead
• Configurable and efficient retry buffer design for low latency and area
• Supports automatic lane reversal and polarity inversion
• Supports the full range of PCIe-defined maximum packet sizes (128B to 4KB) and read request sizes (128B to 4KB)
• Performs PCI Express flow-control credit management, configurable for infinite credits for any traffic type
• Supports legacy INTx, MSI, and MSI-X interrupt semantics
• Configurable filtering rules for posted, non-posted and completion traffic
• Configurable BAR (up to 6) filtering, IO filtering, configuration filtering and completion lookup/timeout
• Support for multiple application clients
• In-band and out-of-band access to configuration space registers and external user application registers with local bus controller
• Expansion ROM, VPD, and Device Serial Number support
• Broad support for optional ECNs, including the latest features, like Unordered IO

Benefits

• Supports all required features of the PCI Express 7.0 (64 128 GT/s) specification
• Allows a full 128GT/s x16 lane bandwidth with up to 1024-bit data path implementations
• Supports advanced RAS data protection features including ECC
• Advanced RAS-DES features for simplified bring-up and debug
• Supports the Synopsys native interface or the optional Arm® AMBA® 5/4/3 AXI application interface
• Configurable for low power, small area and low latency
• Enables efficient embedded DMA applications with Synopsys HyperDMA™
• Standards-compliant Integrity and Data Encryption (IDE) Security Module protects data transfers over PCIe 7.0 interfaces
• TDISP support for PCIe for SR-IOV and hardware security via IDE

Deliverables

• The coreConsultant utility to guide designers through the installation configuration, verification, and implementation of the IP; Verilog RTL code; Example PHY interfaces; ASIC and FPGA synthesis scripts; Verification environment; Synopsys Verification IP for PCI Express; Documentation: release notes, installation/integration guide, application notes, user manual

Technical Specifications