Open silicon IP

The USB 2.0 VMM SystemVerilog VIP is fully documented, off the shelf component for the verification of the USB 2.0 compliant Function Controller.
USB 2.0 VMM VIP is developed using the Synopsys VMM methodology that is used in dynamic simulation of USB 2.0 based design. Verification IP created according to the VMM methodology allows for easy "plug-and-play" use in VMM test benches.

IEEE 1394a-2000 Link Layer Controller eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment.
The IEEE 1394 a-2000 link layer controller (from now on referred to only as 1394a) provides connectionless acknowledged data transfer services between a source node and destination node where node is an addressable device attached to the serial bus with at least a minimum set of control registers.

The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.

A Samsung 11nm Flip-Chip I/O library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBus open-drain cell, 5V OTP cell, 1.8V 3.3V analog cells, and associated ESD.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor.

The CT25207, in combination with the CT25203, implements a complete OPEN Alliance TC14 10BASE-T1S PMD Interface.
The IP also includes a MDIO slave that allows access to Clause 22 PMD standard registers and to IP specific registers (both embedded in the IP) and to custom registers (to be placed outside the IP).

Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible

Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.

Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.

Compliant with M-PHY Spec 3.0
Support HS-MODE Gear3(A/B) with data rate up to 5.8Gb/s, and backward compatible
Support LS-MODE PWM-G1 to PWM-G4 with data rate up to 72Mb/s
Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec

Silicon area: 1073kGates, 174/113 kBytes single-port SRAM (max/min search area configuration)
Synthesizable clock frequency: up to 420 MHz (TSMC65nm LP, topographical synthesis)
Easy back-end: Single clock domain;low number of isolated single port SRAM and clock gating elements; no dual port memories.
Performance configuration: choose internal memory size according to your resolution requirement - up to 1080p.

Open Silicon IP