ONFI IP
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78
IP
from 20 vendors
(1
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10)
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ONFI 5.0 PHY
- The PHY design supports the newly introduced NV-LPDDR4 mode along with SDR, NV_DDR, and NV_DDR2, NV_DDR3 mode.
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ONFI 5.0 Controller
- ONFI v5.0 compliant + Up to 2.4GByte/s.
- All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
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ONFI Flash Controller
- AXI System Interface
- NAND Flash
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
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ONFI 4.0 NAND Flash Controller & PHY
- • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
- • Support standard asynchronous NAND flash
- • High performance from 40MT/s to 800MT/s
- • High density NAND flash up to 1024 Gb
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ONFI 3.2 NV-DDR2 PHY in GDSII
- Compliant to ONFI revision 3.2 standard
- Supports NV-DDR2 mode of operation supporting up to 266MHz or 566MT/s
- Supports NV-DDR mode of operation supporting up to 100MHz
- Supports legacy Asynchronous devices operating from 10MHz to 50MHz
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ONFI 3.2 NAND Flash Controller
- - Compliant to ONFI revision 3.2 standard
- - Supports NV-DDR2 mode of operation supporting up to 200MHz
- - Supports NV-DDR mode of operation supporting up to 100MHz
- - Supports legacy Asynchronous devices operating from 10MHz to 50MHz
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ONFI PHY 4.8GT/s for ONFI v6 & JESD230G
- Multi-interface support: ONFI6.0 up to 4800Mbps
- Multi-data-interface support: CTT (NVDDR3), LTT (NVLPDDR4) and PI-LTT
- Optimized for high performance and integration flexibility. The harden IP included 8-bit data blocks, up to 8 CE/channel, clock blocks, PLL, and DLL.
- High-resolution read/write delay adjust
