ONFI IP

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Compare 91 IP from 26 vendors (1 - 10)
  • Simulation VIP for ONFi
    • Speed
    • NV-DDR3: 800MHz, 1600MT/s (DDR)
    • NV-LPDDR4: 1200MHz, 2400MT/s (DDR)
    • Interfaces
    Block Diagram -- Simulation VIP for ONFi
  • ONFI 3.0 Compatible I/O Buffer on TSMC CLN28HPL
    • High speed, source synchronous, bi-directional I/O buffer supporting the Open NAND Flash Interface (ONFI) 3.0 standard
    • Operation up to 200MHz DDR (400Mbps) performance with single load topology
    • Designed with core and 1.8V IO oxide devices
    • Built-in ODT (On-Die Termination)
  • Open Nand Flash Interface (ONFI) Synthesizable Transactor
    • Compliant with ONFI 2.3/3.0/4.0/4.1/5.0 specifications
    • Supports source synchronous and asynchronous data interfaces
    • Supports all mandatory and optional commands
    • Supports 16 bit bus width operations
    Block Diagram -- Open Nand Flash Interface (ONFI) Synthesizable Transactor
  • Open Nand Flash Interface (ONFI)
    • Compliant with ONFI 2.3/3.0/4.0/4.1/5.0 specifications.
    • Supports Source Synchronous and Asynchronous data interfaces.
    • Supports all mandatory and optional commands.
    • Supports 16 bit bus width operations.
    Block Diagram -- Open Nand Flash Interface (ONFI)
  • ONFI 5.0 Verification IP
    • Compliant to ONFI-2.3 ,ONFI-3.0 ,ONFI-4.0 ,ONFI-4.1 , ONFI-4.2 and ONFI-5.0 specifications.
    • Supports all mandatory and optional commands. Supports generation of Vendor Specific Commands.
    • Supports up to 16-bit bus width operations.
    • Supports implicit and explicit training (DCC, Read DQ, Write DQ Tx, Write DQ Rx).
    Block Diagram -- ONFI 5.0 Verification IP
  • ONFI 5.1 PHY IP
    • Compliant with ONFI 5.1 specification
    • Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s
    • Supports matched or unmatched DQS
    • Supports WDCA/Per-Pin VREFQ Training for NAND devices
    Block Diagram -- ONFI 5.1 PHY IP
  • 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
    • Supports Both NV-DDR3 and NV-LPDDR4 with 4-tap DFEs
    • Support Decision Feedback Equalization (DFE): For extra high loading, DFE can reduce errors and improve data integrity
    • Compliant with JEDEC 6.0 (TBD) and JESD 230G specifications
    • Supports real-time PVT data-eye monitoring
    Block Diagram -- 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
  • Block Diagram -- 3600 ONFI NV-DDR3 and NV-LPDDR4 with Optional DFE
  • ONFI PHY 4.8GT/s for ONFI v6 & JESD230G
    • Multi-interface support: ONFI6.0 up to 4800Mbps
    • Multi-data-interface support: CTT (NVDDR3), LTT (NVLPDDR4) and PI-LTT
    • Optimized for high performance and integration flexibility. The harden IP included 8-bit data blocks, up to 8 CE/channel, clock blocks, PLL, and DLL.
    • High-resolution read/write delay adjust
    Block Diagram -- ONFI PHY 4.8GT/s for ONFI v6 & JESD230G
  • NANDPHY 4.8GT/s for ONFI v6 & JESD230G
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- NANDPHY 4.8GT/s for ONFI v6 & JESD230G
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