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New Wave DV IP

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Compare 16 IP from 4 vendors (1 - 10)
  • FC Upper Layer Protocol (ULP) IP Core
    • FC-AE-RDMA & FC-AV compliant interface with hardware-based offload
    • Hardware DMA engines map sequence data to host memory buffers
    Block Diagram -- FC Upper Layer Protocol (ULP) IP Core
  • Mil1394 GP2Lynx Link Layer Controller IP Core
    • AS5643 compliant interface with hardware-based STOF offload
    • Supports S100/S200/S400 data rates
    • Configurable number of GP2Lynx nodes in a single FPGA
    • Legacy microprocessor or AXI host interface available
    Block Diagram -- Mil1394 GP2Lynx Link Layer Controller IP Core
  • Mil1394 OHCI Link Layer Controller IP Core
    • AS5643 compliant interface with hardware based STOF offload
    • Supports S100/S200/S400/S800/S1600/S3200 data rates
    • Configurable number of OHCI nodes in a single FPGA
    • AXI-based host interface for embedded or PCIe based processors
    Block Diagram -- Mil1394 OHCI Link Layer Controller IP Core
  • 1394b PHY IP Core
    • AS5643 compliant interface
    • Supports S100 / S200 / S400 / S800 / S1600 / S3200 data rates
    • Complete PHY layer implementation
    Block Diagram -- 1394b PHY IP Core
  • Fibre Channel ASM (Anonymous Subscriber Messaging) Core
    • Message label validation checks performed in hardware
    • Multiple user modes for receiving messages, including strictly mapped message-to-buffer and free-buffer implementations
    • Transmit message chaining options provided
    • Complete set of registers for managing core and configuring core options
    Block Diagram -- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
  • Block Diagram -- HOTLink II IP Core
  • High Speed Data Bus (HSDB) IP Core
    • Complete PHY and Mac layer hardware implementation for HSDB.
    • Provides an easy-to-integrate frame interface. F-22 compatible interface implementation. 
  • Ethernet Real-Time Publish-Subscribe (RTPS) IP Core
    • OMG DDSI-RTPS 2.2 compliant interface with hardware-based offload
    • Hardware DMA engines with message label mapped buffers
    • Message label validation and filtering
    • Host processor offloaded from all networking responsibilities
    Block Diagram -- Ethernet Real-Time Publish-Subscribe (RTPS) IP Core
  • ARINC 818 Streaming IP Core
    • Flexible video pixel bus input with synchronization signals (video_active, vsync, hsync) that supports a wide range of pixel depths and number of parallel pixels
    • Compatible with all FC line rates up to 10G (incl. non-standard rates)
    • Core handles synchronization and clock crossing into the FC clock domain. User clock can be asynchronous to the FC clock
    • Automatic creation and maintenance of the Object 0 and container header
    Block Diagram -- ARINC 818 Streaming IP Core
  • ARINC 818 Direct Memory Access (DMA) IP Core
    • ARINC 818-2 compliant interface
    • Supports data rates up to 10G with 8b/10b encoding
    • Hardware-based container processing
    • Hardware DMA engines with ARINC 818 container mapping
    Block Diagram -- ARINC 818 Direct Memory Access (DMA) IP Core
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