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Search (243)
Compare 243 IP from 14 vendors (1 - 10)
  • MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    Block Diagram -- MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
  • MIPI DPHY & LVDS Transmit Combo on GF55LPe
    • MIPI D-PHY version 1.2 compliant PHY transmitter
    • OpenLDI version 0.9 compliant LVDS transmitter
    Block Diagram -- MIPI DPHY & LVDS Transmit Combo on GF55LPe
  • MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
  • MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
  • High speed NoC (Network On-Chip) Interconnect IP
    • High Performance
    • Low Power Consumption
    • Smaller Area
    Block Diagram -- High speed NoC (Network On-Chip) Interconnect IP
  • DDR multiPHY IP
    • Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
    • When combined with a Synopsys Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
    • Scalable architecture that supports from 0 to 1066 Mbps
    • DFI 2.1 interface to controller
    Block Diagram -- DDR multiPHY IP
  • Gen 2 DDR multiPHY IP
    • Support for JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR3-2133
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell components allows precise control of timing critical delay and skew paths
    Block Diagram -- Gen 2 DDR multiPHY IP
  • DDR3/2 PHY - TSMC 40LP25
    • When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
    • Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
    • Support for DDR3L (1.35V DDR3)
    • Support for DDR2 and DDR3 DIMMs
    Block Diagram -- DDR3/2 PHY - TSMC 40LP25
  • DDR4 multiPHY SP - SS 14LPP
    • Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR4-2667
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
    Block Diagram -- DDR4 multiPHY SP - SS 14LPP
  • DDR4 multiPHY - UMC 28HPC18
    • Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR4-2667
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
    Block Diagram -- DDR4 multiPHY - UMC 28HPC18
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