IP Catalog > NAND Flash Controller

NAND flash controller IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (45)
Compare 45 IP from 24 vendors (1 - 10)
  • NAND Flash Controller - Ensures robust NAND Flash interface validation for reliable designs
    • The NAND Flash Controller Verification IP (VIP) is a specialized tool for validating and simulating NAND Flash memory interfaces in System-on-Chip (SoC) designs. It ensures compliance with protocols, error correction, and optimal performance across varied conditions.
    • This versatile tool supports a wide range of applications, including automotive, consumer electronics, industrial automation, and aerospace. By guaranteeing reliable integration of NAND Flash memory, it enables seamless functionality in devices ranging from gaming consoles to mission-critical systems
    Block Diagram -- NAND Flash Controller - Ensures robust NAND Flash interface validation for reliable designs
  • ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
    • ONFI v5.0 compliant + Up to 2.4GByte/s.
    • All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
    • Wide hardware support + Four 8-bit data paths + 8 NAND targets each + Data bus inversion.
    • Full PLL support + PLL within PHY + 10MHz SDR + 1.2GHz NV-LPDDR4 + Everything in between
    Block Diagram -- ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
  • NAND Flash Controller
    • The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips.
    • It is designed with scalability in mind and provides standard AXI interface for the ease of integration in SoC design.
    • The NFC has many configurable features to support the requirements for different NAND Flash applications.
    Block Diagram -- NAND Flash Controller
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
  • Nand Flash Controller
    • Simple streaming interface towards user logic for data read and write
    • Commands supported towards NAND Flash Memory:
    • ECC Logic: Hamming code used to correct 1-bit error and detect 2-bit errors
    • Commands supported from user: Block Erase, Read, Program and Copy-Back Program
    Block Diagram -- Nand Flash Controller
  • NAND Flash Controller
    • Highly Integrated IP Offering
    • Speeds system integration and reduces design cost
    • Command and Data DMA
    • Reduces software overhead
    • Wide Support of Standards
    • Enables system flexibility
  • ONFI 4.0 NAND Flash Controller & PHY
    • • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
    • • Support standard asynchronous NAND flash
    • • High performance from 40MT/s to 800MT/s
    • • High density NAND flash up to 1024 Gb
    Block Diagram -- ONFI 4.0 NAND Flash Controller & PHY
  • ONFI 2.3 NAND Flash Controller
    • Compliant to ONFI 2.3
    • Supports speed ranging from 40MB/s to 200MB/s
    • Supports synchronous modes
    • Supports asynchronous mode [0-5]
    Block Diagram -- ONFI 2.3 NAND Flash Controller
×
Semiconductor IP