NAND Flash Controller has a built-in AHB Slave Interface, handles all sorts of Nand Flash commands, address & data sequences. It allows the users to access the NAND flash memory simply by reading or writing into the Operational registers & the data buffer.
It consists of four major blocks:
- AHB Slave I/F: It consists of the AHB FSM & Operational registers.
- Synchronization Module (Sync): This block has handshake logic to communicate with the AHB interface and with the flash interface. To increase the throughput a single page size buffer is used for the data transactions.
- Error Correcting Code (ECC): This block generates & compares ECC (user programmable) for every page program & page read to/ from the Nand Flash respectively. It uses Hamming Code algorithm for single bit error correction and two or more bit error detection (SECDED). It calculates 28 bit ECC for every 512 word data.
- NAND Flash Interface: This block handles all sorts of Nand Flash commands, address, data sequences, and manages all the hardware protocols & flash timing requirements.
AHB Compliant Nand Flash Controller
Overview
Key Features
- Flash Side Features
- Supports up to 2Gb Nand Flash devices.
- Supports 3/4/5 address cycles.
- Supports 8/16 bits of Flash I/O bus sizes (user programmable data transfer mode).
- Programmable R/W pulse timings (RE#/ WE# pulse width)
- Configurable Flash timing (Twhr, Trr delays).
- Double protection for page program & block erase.
- Support multiple page program & Read operation.
- Same data can be programmed to successive pages without host having to supply data for each page.
- ECC protection by programming Configuration register (user programmable).
- 28 bit ECC for 512 word data.
- Hamming Code algorithm for Single bit error correction and two or more bit error detection (SECDED)
- Command, flash address and buffer address Error logging in Status register.
- Multi-page program/ read operation termination on detection of ECC error at intermediate page with generation of Interrupt & setting of Error in Status register
- Block address logging in Status register on detection of ECC or program/ erase Error.
- Host Side Features
- AHB slave interface compliant to AMBA Specification (2.0)
- 32 bit input & output buses.
- Supports Byte, Half word and Word transactions.
- Supports all Incremental AHB Burst transactions (i.e. INC, INC4, INC8 and INC16)
- Supports OK, ERROR and RETRY responses.
- Random access to any location of internal page buffer by the host.
- Supports two modes of operation-boot & normal mode.
- Supports system booting from Nand Flash in boot mode.
Deliverables
- Verilog RTL/Synchronous Design
- Test Plan, Test Bench ,Test Cases & Test Results
- Technical Reference Manual, Architecture/ LLD Doc
- ISE Synthesis Scripts
Technical Specifications
Foundry, Node
90nm
Maturity
Soft Core
Availability
Now
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