Multi-Standard SerDes IP

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Compare 3 IP from 3 vendors (1 - 3)
  • Multi-Standard SerDes PHY
    • Configurable parallel data rate of 8 /10 / 16 / 20 / 32 / 40 / 64 / 80
    • Input reference 5MHz to support 2.5/5/10G data rates
    • Tight control over termination resistor (~50 Ohm) with on chip calibration
    • Tight skew control of 1UI between lanes of the PMA
    • Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
  • 4.25 Gbps Multi-Standard SerDes
    • The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.
    Block Diagram -- 4.25 Gbps Multi-Standard SerDes
  • 20G MSS (Multi-standard SerDes) PHY
    • Developing under SF4X CMOS technology (2025.06.30 MTO)
    • Compliant to multiple standards, max datarate 20Gb/s
    • Channel Configuration for Data Lanes: 1, 2 or 4 Data Lanes
    • Reliable Ring OSC PLL based architecture for Low power consumption
    Block Diagram -- 20G MSS (Multi-standard SerDes) PHY
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Semiconductor IP