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Microsemi IP

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  • Error Detection and Correction
    • Microsemi FPGA-optimized RTL core generator
    • Two modes:
    • EDAC with internal RAM
    • EDAC encoder and decoder generation
    Block Diagram -- Error Detection and Correction
  • Flash Memory Endurance Extender / EEPROM Emulation
    • Support EEPROM Emulation and Flash Memory in the Same Application
    • Support Flash Memory and Flash Memory with Endurance Extension in the Same Application
    • Available EEPROM Configuration Sizes (in Bytes): 128, 256, 512, 1024, and 2048
    • Configurable Endurance Size from 1 to 128 Pages in Power of 2 Increments (i.e., 1, 2, 4, ..., 128)
    Block Diagram -- Flash Memory Endurance Extender / EEPROM Emulation
  • Simple Micro APB Bus Controller
    • Programmable APB bus controller
    • Hard, soft (RAM), or NVM instruction storage on Fusion devices; hard instruction storage on SmartFusion2, IGLOO2, RTG4, and PolarFire devices; hard or soft instruction storage on other device families
    • Automatic detection of CoreAI in CoreABC’s APB address space and auto-creation of analog configuration MUX (ACM) data, based on CoreAI configuration
    • Extensive configurability, allowing very low cost and resource efficient implementations
    Block Diagram -- Simple Micro APB Bus Controller
  • Cascaded Integrator-Comb filters
    • Fixed or programmable rate change from 2 to 1024
    • One to eight integrator-comb stages
    • Comb differential delay of one or two
    • Signed 2's complement input data
  • On-chip APB SRAM Memory Controller
    • Optimized for use with Microsemi Flash FPGAs
    • Implements Standard Slave APB Bus Hardware Interface
    • 32-Bit Interface, Allowing Byte, Halfword, or Word Accesses to SRAM
    • Interfaces to Synchronous or Asynchronous SRAM
  • On-chip Nonvolatile APB Memory Controller
    • Fully AMBA 2 APB-compliant
    • Compatible with AMBA 3 APB
    • Multiple memory sizes and variable number of NVM blocks
    • Configurable 8-, 16-, or 32-bit data bus size
  • FROM Memory Access Controller
    • Allows FROM access from software
    • APB bus interface
    • Small size - as small as 20 tiles
    • Easy to use
  • On-chip AHB SRAM Memory Controller
    • Optimized for use with Microsemi Flash FPGAs
    • Implements Standard Slave AHB Bus Hardware Interface
    • 32-Bit Interface, Allowing Byte, Halfword, or Word Accesses to SRAM
    • Interfaces to Synchronous or Asynchronous SRAM
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