MIPI I3C Master RISC-V based subsystem

Overview

RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors. All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface.

Key Features

  • Dynamic address assignment.
  • Host controller compliance
  • SDA arbitration.
  • Data transfer with and without broadcast.
  • All basic CCC command features.
  • Both push-pull and open drain mode transaction.
  • Private write and read operations.

Block Diagram

MIPI I3C Master RISC-V based subsystem Block Diagram

Technical Specifications

×
Semiconductor IP