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Memory Controller IP

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Compare 1,248 IP from 124 vendors (1 - 10)
  • NAND Memory Controller
    • The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode.
    • This core also supports error correction on the fly without any processor intervention. Up to 8 memory chips can be accessed on the same bus with write speed of 100Mbps and read speeds of 120Mbps.
  • High-Performance Memory Controller II SDRAM Intel® FPGA IP Core
    • The High-Performance Memory Controller II SDRAM Intel FPGA IP core handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 933 MHz
    • The intellectual property (IP) core initializes the memory devices, manages SDRAM banks, translates read-and-write requests from the local interface into all the necessary SDRAM command signals, and performs command and data reordering.
    Block Diagram -- High-Performance Memory Controller II SDRAM Intel® FPGA IP Core
  • xSPI Multiple Bus Memory Controller
    • SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.
    • JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.
    Block Diagram -- xSPI Multiple Bus Memory Controller
  • HBM Memory Controller
    • Low latency, high bandwidth
    • Supports HBM or DDRx memory types
    • 16 parallel access channels
    • Multi, independent internal queues
    Block Diagram -- HBM Memory Controller
  • HBM4 Memory Controller
    • Supports HBM4 memory devices
    • Supports all standard HBM4 channel densities (up to 32 Gb)
    • Supports up to 10 Gbps/pin
    • Refresh Management (RFM) support
    • Maximize memory bandwidth and minimizes latency via Look Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM4 Memory Controller
  • GDDR7 Memory Controller
    • Supports up to 40 Gbps per pin operation
    • 2.5 GHz CK4 clock
    • 1.25 GHz controller clock
    • Internal data path 32x memory width (i.e. 256 bits for 8-bit memory)
    • Optimized for high efficiency and low latency across a wide range of traffic scenarios (random/sequential, short/long bursts, etc.)
    • Optimized command sequence for highest bus utilization including per-bank refresh scheduling: single queue structure handles look-ahead activates/ precharges and read/write ordering for minimal latency
    Block Diagram -- GDDR7 Memory Controller
  • LPDDR5X DDR Memory Controller
    • JEDEC LPDDR5X/LPDDR5 devices compatible
    • Data rates up to 8533Mbps
    • Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
    Block Diagram -- LPDDR5X DDR Memory Controller
  • DDR3 SDRAM Memory Controller
    • Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
    • Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
    Block Diagram -- DDR3 SDRAM Memory Controller
  • HBM3 Memory Controller
    • High Bandwidth Memory (HBM) DRAM controller
    • Supports AXI 4.0 port
    • Supports DFI1: 2
    • Supports BL8
  • HBM3E/3 Memory Controller
    • Supports HBM3E / HBM3 memory devices
    • Supports all standard HBM3 channel densities (up to 32 Gb)
    • Supports up to 9.6 Gbps/pin (HBM3E) or 8.4 Gbps/pin (HBM3)
    • Refresh Management (RFM) support
    • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM3E/3 Memory Controller
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