The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode. This core also supports error correction on the fly without any processor intervention. Up to 8 memory chips can be accessed on the same bus with write speed of 100Mbps and read speeds of 120Mbps. Support for Linux OS is already implemented and it is included with the IP core, alowing to use UBIFS and JFFS. The design is already optimized and tested for all Novo Space's products including Microchip SmartFusion2® and Xilinx Zynq UltraScale+®
This IP core comes in different versions:
- AXI/AXILite: Ready to connect to a AXI/AXILite bus. It has a AXILite slave to be configured and a AXI full interface to read/write data from memory
- AHB/APB:Same concept as AXI/AXILite configuration but with APB slave for configuration and AHB to write memory
SPECIFICATIONS
| NV-DDR I/O | No |
| Multi chip/lun | Up to 8 |
| Onfi version | 2.1 |
| Page/OOB size | Configurable to support any NAND chip |
| ECC Algorithm | Configurable Hamming code depending on chip specs (typically Hamming (72,64)) |