MIPS IP

• Reliable event driven computing is enabled by the unique MIPS M8500 real-time multithreaded architecture.
• The M8500 is an easy-to-use general-purpose microcontroller with advanced efficiency and performance for sub -10μs control loop algorithms.
• The M8500 is a turnkey closed loop control solution with functional safety options and end-to-end software solution.

• Flexible Models: Bring your physical AI application, open-source, or commercial model
• Easy Adoption: Based on open-specification RISC-V ISA for driving innovation and leveraging the broad community of open-source and commercial tools
• Scalable Design: Turnkey enablement for AI inference compute from 10’s to 1000’s of TOPS

• Industrial Networking: Rapid packet processing of data through multiple, switched ethernet ports with support for factory automation protocols
• 5G/6G Communications: Scalable L2/L3 Ethernet switch with flexible port counts/speeds, including TSN and security
• Automotive Gateway: High-speed data packet networking with multiple communication interfaces and support for switching and bridging
• Datacenter Infrastructure: Standalone data processing units to handle highly multiplexed data streams corresponding to millions of network connections with high efficiency and low power

• The only Multi-Threaded Out-of-Order RISC-V Core with ASIL-B Certification
• Highly scalable multi-core, multi-cluster, coherent computing solution
• MIPS extensions for improved performance and functionality
• Use in Automotive, Datacenter, and Embedded applications

• Efficient throughput with the first RISC-V core to support up to 4-way multithreading
• Highly scalable multi-core, multi-cluster coherent computing solution
• MIPS Enhancements for increased connectivity and throughput
• Use in 5G/6G Comms Infrastructure, Automotive Gateways, Embedded & Datacenter

• Object code compatible with MIPS' R2000
• Fully synchronous design
• No microcode; All control via state machines
• Simple synchronous interface to memory and peripherals

• Designed for ASIC and PLD implementations.
• Fully static design with edge triggered flip-flops.
• Supports MIPS microprocessors.
• Fully integrated single chip design provide complete system level functions for all external data access.

• The BSi13000 series comprehensive support of the latest version of Bluetooth LE specifications (v5.4), 2Mbps, Long Range, Isochronous / LE Audio, Packet Advertising with Response, and Channel Sounding.
• The advanced topologies including concurrent master/slave operations and support for the scalable multiple connections.

• GEON-SoC is an area-efficient, processor-agnostic, hardware root of trust for SoC designs.
• It implements secure boot and can optionally be enhanced to support firmware decryption and secure debug, or to act as a post-boot hardware security module (HSM).

• The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the Avalon System Interconnect Fabric to an I2C Bus.
• The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.

The DB-I2C-S-AVLN is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices. Figure 1 depicts the system view of the DB I2C-S-AVLN Controller IP Core embedded within an integrated circuit device.