MIPI D-PHY TSMC 28nm HPC IP
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MIPI D-PHY/sub-LVDS Transmitter - 8-Lane 2.5Gbps - TSMC 28nm HPC+
- The CL12661M8T1KM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
- The CL12661M8T1KM2JIP is designed to support data rate in excess of maximum 2.5Gbps utilizing sub-LVDS / MIPI-DPHY interface specification.
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Camera Combo Receiver - 2.5Gbps 8-Lane - TSMC 28nm HPC
- The CL12832M8R2JM3QIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
- The CL12832M8R2JM3QIP2500 is designed to support data rate in excess of maximum 2.5Gbps utilizing SLVS-EC / MIPI D-PHY v-1.2/ CMOS 1.8V interface specification.
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Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC
- The CL12842M8R2JM4TIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
- The CL12842M8R2JM4TIP2500 is designed to support data rate in excess of maximum 2.5Gbps utilizing SLVS-EC / sub-LVDS / MIPI D-PHY v-1.2/ CMOS 1.8V interface specification.
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Camera MIPI D-PHY Receiver 4.5Gbps 4-Lane
- The CL12632M4R1AS1BIP4500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
- The CL12632M4R1AS1BIP4500 is designed to support data rate in excess of maximum 4.5Gbps utilizing MIPI D-PHY v2-1 interface specification.
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Camera Combo Receiver - 5.0Gbps 8-Lane
- The CL12822M4R2JM2LIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
- The CL12822M4R2JM2LIP5000 is designed to support data rate in excess of maximum 5.0Gbps utilizing SLVS-EC ver.2.0 / MIPI D-PHY v2-1 interface specification. The CL12822M4R2JM2LIP5000 can change Interface type to same PAD for changing mode.
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Camera 6/7-mode Combo Receiver - 1G/1.5Gbps
- The CL12684KM4-8-12-16R3AM6-7ZIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
- The CL12684KM4-8-12-16R3AM6-7ZIP is designed to support data rate in excess of maximum 1Gbps utilizing sub-LVDS / mini-LVDS / LVDS / HiSPi(SLVS-400, HiVCM) / MIPI-DPHY / CMOS-1.8V / CMOS-3.3V interface specification.